I spent a fair amount of time getting back to speed with the TMS99105 project. I have in the meantime advanced my own TMS9900 VHDL core. This sister project by now had a more compatible version of the TMS9918 video processor, and a little different memory map from the TMS99105 version.

As a reminder: In principle my two projects are almost identical, running on the same Pepino FPGA board, the only major exception being that the first version of the TI-99/4A clone uses the TMS99105 physical CPU chip on an external daughterboard, while my latter project is the same, but replaces the TMS99105 chip with my own version of the TMS9900 core, thus integrating it to the FPGA. As I have been working on this project more lately, it has gotten more advanced.

Nearly all of the VHDL files are identical between the two projects, the obvious differences being a different top-level module, integrating either the TMS99105 external CPU or the TMS9900 core as a VHDL module.

Enough of background - the difference that prevented me from running the Megademo on the TMS99105 system was that this version had an older version of the memory map, and did not support a "ROM" cartridge of 512K which is a requirement for the Megademo. To be more precise the Megademo comes in different versions, but the one of interest to me is the one that requires 512K of paged ROM space - and I provided that in the latter project by rearranging how the 1MB external memory of the Pepino board was divided between different functions.

I ran into great difficulty in simply copying the same memory layout over from the TMS9900 core system. After some intense head scratching I determined that the seeming insignificant memory map change resulted consistently in timing problems, making the TMS99105 system very unstable. For now I solved this problem by just bypassing the memory paging unit, therefore limiting the addressable RAM to 32K, down from 256K of paged memory while simultaneously allowing for a 512K ROM area to exist. The ROM area is paged too, having 64 pages of 8K in size, but this paging mechanism is very simple compared to the RAM paging system. The RAM paging seems to be on the critical path.

To cut long story short, with 512K of ROM space I was able for the first time to run the Megademo with the TMS99105 CPU. On real TI CPU iron, with my FPGA implementation of the rest of the TI-99/4A. Needless to say, it runs very fast, having about 7x the processing power of the original TI-99/4A. The most interesting aspect of this test of running the demo for me was that the TMS99105 version has the exact same problems as shown when using my own processor core. Most of the demo runs just fine, but a couple demo sections still show graphics glitches and towards the end the demo gets stuck. This proves to me that my TMS9900 clone is now getting "very" compatible, and that most likely the problems I am encountering now in the demo are due to 1) my TMS9918 video processor clone still having compatibility issues and 2) the place of the demo where execution gets stuck is likely due to poor implementation of some TI-99/4A feature used by the demo but not relating to graphics (smells like TMS9901 timer interrupt to me).