Close
0%
0%

8-bit TTL computer

Designing and building my own 8-bit TTL computer from scratch

Similar projects worth following

Having completed building my version of Ben Eater's 8-bit breadboard computer nearly a year ago, building my own Apple 1 clone, building and looking into the inner workings of the Gigatron kit and studying the book Digital Computer Electronics it is finally time to design and build my own TTL computer from scratch!

The main goal is to learn how to do this and see if I can actually accomplish this build. The computer itself must be usable as a learning tool for people that want to learn about CPU architecture.
That means lots of blinking lights and switches!

The plan is to build an 8-bit computer with TTL logic chips that supports 64 kB of memory and a clock speed up to 1 MHz. The first project log on Architecture describes the features in a bit more detail.

All the circuits are (being) designed in KiCad and then prototype'd on breadboards. When the whole thing has come to live and the entire design has been proven to work, I'll design a PCB for it as well.

I will try to regularly update the project log with the status of the project.
At the moment I'm still in the design phase, although a lot has taken shape by now:

  • I worked out an architecture (see project log)
  • Worked out the majority of instructions, including their T-states (coming to project log once tested)
  • Worked out several of the circuits (coming to project log as modules are tested)
  • Built the clock module and one register on breadboard (coming to project log soon)
  • Keeping track of everything in a Github repository.

  • Updated architecture & instruction set

    Ruud van Falier05/08/2018 at 11:49 0 comments

    In the past weeks I have prototyped small parts of the computer, thought things over and realized that I had to make a few adjustments to the architecture and instruction set.

    Let me start with the progress that was made with the circuit diagrams.  The following diagrams have been completed and some of them are tested:

    • Clock [tested]
    • Program counter
    • A, B, C, D & Flags register [tested]
    • ALU [partially tested in Logisim]

    The following changes have been made to the architecture:

    • The X & Y registers have been renamed to C & D, nothing shocking here.
    • The ALU now has it's own internal accumulator register.
    • Input for the ALU can now come from the A, C & D register (and not just fixed from the A register). The second operand still comes from B.
    • Two outputs are now accounted for: decimal display (output 1) and serial (output 2)


    The instruction set has a few new and updated instructions:

    MOV [A,B,X,Y] [A,B,X,Y] Copy register N2 to register N1
    MVI [A,B,X,Y] #value Copy immediate value to register N
    LD [A,B,X,Y] $address Load register N with value at memory address
    ST [A,B,X,Y] $address Store register N value at memory address
    ADD [A, X, YN + B → N
    ADC [A, X, YN + B + 1 → N
    SUB [A, X, Y] N - B → N
    SBC [A, X, Y] N - B - 1 → N
    AND [A, X, Y] N & B → N
    OR [A, X, Y] N | B → N
    XOR [A, X, Y] N ⊕ B → N
    NOT [A, X, Y] !NN
    INC [A, X, Y] N + 1 →
    DEC [A, X, Y] N - 1 →
    SHL [A, X, Y] Shift all bits in register N to the left
    SHR [A, X, Y] Shift all bits in register N to the right
    RAL [A, X, Y] Rotate all bits in register N to the left
    RAR [A, X, Y] Rotate all bits in register N to the right
    CMP [A, X, Y]Compare register N to register B
    JMP $address Jump to memory address
    JZ $address Jump to memory address if zero flag is set
    JNZ $address Jump to memory address if zero flag is not set
    JC $address Jump to memory address if carry flag is set
    JNC $address Jump to memory address if carry flag is not set
    JEQ $address Jump to memory address if N = B
    JLT $address Jump to memory address if N < B
    JGT $address Jump to memory address if N > B
    CALL $address Jump to subroutine at memory address
    RET Return from subroutine
    NOP Do nothing
    HLT Halt execution
    IN Load data from input into register A (needs to be worked out)
    OUT [1, 2] [A, B, X, Y] Output data from register N2 on output N1
    (1 = decimal display, 2 = serial output)

    I'm currently waiting on more breadboards coming in for prototyping and slowly working out all the circuit diagrams in the meantime.

    More updates coming soon!

  • Instruction set

    Ruud van Falier04/29/2018 at 11:37 1 comment

    I've done a bit more work on defining the instruction set.
    These are the instructions that I'm planning to implement and that should be supported by the architecture that has been worked out so far:

    MOV [A,B,X,Y] [A,B,X,Y] Copy register n1 to register n2
    MVI [A,B,X,Y] #value Copy immediate value to register n
    LD [A,B,X,Y] $address Load register n with value at memory address
    ST [A,B,X,Y] $address Store register n value at memory address
    ADD A + B → A
    SUB A - B → A
    AND A & B → A
    OR A | B → A
    XOR A ⊕ B → A
    INC A + 1 → A
    DEC A - 1 → A
    RAL Rotate all bits in register A to the left
    RAR Rotate all bits in register A to the right
    JMP $address Jump to memory address
    JZ $address Jump to memory address if zero flag is set
    JNZ $address Jump to memory address if zero flag is not set
    JC $address Jump to memory address if carry flag is set
    JNC $address Jump to memory address if carry flag is not set
    CALL $address Jump to subroutine at memory address
    RET Return from subroutine
    NOP Do nothing
    HLT Halt execution
    IN Load data from input into register A (needs to be worked out)
    OUT Output data from register A (needs to be worked out)

    I haven't given much thought to input & output yet, so I might need a few specialized instructions in the future to cover that part.

  • Architecture

    Ruud van Falier04/27/2018 at 19:53 0 comments

    Most of the computer's architecture has been worked out (at least on paper...)
    Here is a schematic overview of the entire architecture:

    [View Architecture Overview]

    Let me explain what I have in mind:

    • There is an 8-bit data bus and all the registers are 8-bit.
    • 64 kB of memory can be accessed using a 16-bit address bus, managed by the memory access register.
    • The memory consists of 16 kB ROM and 48 kB RAM.
    • The program counter is 16-bit and can be loaded using the X and Y register.
      The program counter output can be loaded into the memory access register.
    • The X and Y registers can also be used to load a 16-bit memory address directly into the memory access register.
    • The A(ccumulator), B, X and Y registers can all be used to read and write to the data bus.
    • I'm going with the 74181 for the ALU (which some will consider to be a shortcut).
    • Input for the ALU comes from the Accumulator and B register, output is put on the data bus.
    • The stack pointer is used while storing return addressed for CALL instructions. It's basically a 4-bit binary counter and the module outputs 16-bits in total of which the first 12-bits are always set to 1 and last 4 bits come from the counter. This means the stack is stored at FFF0-FFFF in RAM. Considering the fact that memory addresses take up 2 bytes, the stack allows for up to 8 nested subroutine calls.
    • The ROM can be disabled. I want to be able to use this computer for educational purpose and have the option to manually put a program and RAM (using switches) instead of always booting from ROM.
    • For the same educational purpose, but also for debugging purpose, the clock can run in several modes: single-step, slow variable mode (1 to 15 Hz) and turbo mode (1 MHz).
    • Functionality for input and output modules still has to be determined.
    • The computer will be driven by micro code. The instruction set is still under construction.
    • Instructions consist of 1 to 3 bytes: 8-bit opcode and 16-bit data.

    I really want to be able to use this machine to teach others about CPU architecture.
    I'm planning to add LED indicators to all the modules in order to visualize the data flow.
    Aside from that the machine can be single stepped and programs can be loaded straight into RAM using switches.

View all 3 project logs

Enjoy this project?

Share

Discussions

roelh wrote 04/28/2018 at 08:34 point

Hi Ruud,  nice project !  

I suggest that you first make a simulator and write a few small programs. That might point to things that can be improved in the architecture or microcode. In my https://hackaday.io/project/11012-risc-relay-cpu I changed the instruction set four times., because I missed certain instructions during programming.

  Are you sure? yes | no

Ruud van Falier wrote 04/28/2018 at 10:43 point

Hi Roel, thanks!

Very good advice on the simulator, I will definitely take that into consideration. I will also take a look at your project and see if I can take some learnings from that.

  Are you sure? yes | no

Similar Projects

Does this project spark your interest?

Become a member to follow this project and never miss any updates