RGGBer - open hardware for embedded vision

RGGBer is a FPGA based complete development kit dedicated to embedded vision

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RGGBer is a FPGA based complete development kit dedicated to embedded vision. It provides users all the necessary hardware resources and interfaces to quickly build up image capture and processing system. As a standard hardware platform, RggBer is able to free designers from spending time on general, repetitive basics of embedded vision developments and concentrate energy on the featured things.
The campaign page is now live on

In order to let people know well and deeply about RggBer hardware and how it satisfy user’s development, we new created several separate projects in below links:

RggBer is a full open source hardware product. You may find all the necessary design resources on github site.

We set up very clear design criteria prior to the designs. RggBer must:

  1. Able to capture full color images in real time up to 1080p, 60Hz
  2. Able to receive full color digital video streams up to 1080p, 60 Hz
  3. Able to transmit full color digital video streams up to 1080p, 60 Hz
  4. Able to provide adequate bandwidth for frame buffering
  5. Extensible for future functions and formats
  6. Accessible via multiple interfaces
  7. Easy to assemble and integrate as needed
  8. Affordable
  9. Fully open in terms of documentation and source code

The top level hardware diagram shown below satisfies these criteria.

The main RggBer hardware consists of one FPGA core board and one image based board. The FPGA core-board connects to the imaging base-board via two high-speed, board-to-board connectors. It provides user I/O to the FPGA, PLL clock outputs, and dedicated global clock inputs for future expansions. The board level hardware diagram is shown below:

RggBer’s dual board design has several advantages:

  • Space savings.
  • The imaging base-board can be easily updated to support an alternative display port, 4K resolution, and other new video technology.
  • The FPGA core-board can be used for other FPGA-based projects, such as digital signal processing or multi-axis motor control.

The schematic and BOM of these two boards are open to users.

FPGA core board

Image base board

A : borad to board connector, FG : HDMI output, type CM : HDMI input, type C
B : USB2.0 and +5VH : iXCtrl interface N : SD card interface
C : FPGA JTAG interfaceI : MCU C2 interfaceO : HDMI RX chip
D : iXHis interfaceJ : MCU chipP : mini USB, +5V
E : FPGA chipK : HDMI TX chipQ : BL4.0 module
F : DDR2 chipL : borad to board connector, MR : iXCIS interface

Board to Board connectors pin definition

RggBer main chips are shown here:

FPGA28848 LEs, 594Kbs embedded memory, 66 18x18 multipliers, 4 PLLs, support DDR2 up to 200Mhz.
DDR22Gbits, 2 chips x 16bits x 64M x 400Mhz, up to 12Gbps.
MCU32K flash, (2K+256) sram, 50Mhz, 12bits ADC, 12bits DAC.
HDMI TX chipVideo only, pixel rate 165Mhz, 1080p and WUXGA at 60Hz, RGB 24bits
HDMI RX chipVideo only, pixel rate 165Mhz, 1080p and WUXGA at 60Hz, RGB 24bits
BLE4.0 moduleBluetooth to UART module

RggBer provides three I/O interfaces: iXHis, iXCIS and iXCtrl. You can use them to expand RggBer’s application support and functionality.

iXHis is the interface that supports high speed channels. It uses a 50-pin FFC connector to easily connect to a USB3.0 bridge chip, an ultra high-speed image sensor, a second channel HDMI receiver, Gige PHY chip and camera-link, etc.

iXCIS is the interface that supports a standard DVP port. Via this 24 pin FFC connector, RggBer can connect to various mainstream image sensors and ISP chips.

iXCtrl is a 10-pin FFC connector that provides basic control capabilities, such as LED control, temperature control, and other PWM based controls. This allows RggBer to work in stand-alone machine vision applications.

View project log

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[this comment has been deleted]

Jie Zou wrote 08/02/2017 at 03:49 point

what you see on nowaday github repos is rev 3 hardware which you may find some footprint issues. We may update to rev 4 after successfully meet the campaign goals. Then rev 4 gerber files will be uploaded to repos. Here we just warn up the project in communities!

Again, most of the followers are interesting in FPGA framework and video processing RTL code which are core value of RGGBer.  

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EngineerAllen wrote 08/05/2017 at 18:56 point

ok good job :)

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Robert Walczyk wrote 10/14/2016 at 22:45 point

Hi Jie,

This is great work! I'm really impressed with your demos. If the RTL is open, I would really like to contribute with some image processing techniques. Let me know if you're interested.
All the best,

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Jie Zou wrote 10/15/2016 at 06:07 point

Hi Robert:

    Welcome to join the project! RggBer is created as a standard hardware platform for various image processing implement. As a typical open hardware, the RTL code and other design documentations will be shared, for example on github. We create the framework in FPGA as pipleline structure, so that your processing modules are easily insert in the stream. You are welcome to contribute anything you love. Next week, we will start to update the project by logs every 2-3 days here. The 1st update might be a HDMI based 1080p graphic card, with video and more still images. Enjoy...

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Robert Walczyk wrote 10/15/2016 at 22:45 point


Let me know when the RTL will be available on GitHub, I promise to add my 2 cents ;) 


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Jie Zou wrote 10/16/2016 at 04:12 point

Sure. Let's keep moving.

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ch.dugasduvillard wrote 10/07/2016 at 08:06 point


Your project is incredible!

How do you manage the HDCP on HDMI ?

Would it be possible to reduce your card to :

- 1 HDMI Input ,(peraps more?)

- Add WIFI (or Ethernet Input)

- Bluetooth

- 1 HDMI Output

The goal would be to overlay the source, and display other information from internet, like mail, tweet.. other 


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Jie Zou wrote 10/07/2016 at 10:34 point

Nice to see your comments..

TFP401 and TFP410 which are used as HDMI RX and TX on RggBer do NOT have HDCP engines. TFP501 and TFP510 do have.

These are 3 extension interfaces, iXCIS, iXHis and iXCtrl. iXHis supports both LVDS mode and single-ended mode. It is able to extend addtional HDMI RX adaptor by iXHis port. 

WIFI, Ethernet is also able to be implement by iXHis. User need to create a adaptor for these.

I have a concept of HDMI hub device by RggBer. 4 inputs of HDMI stream and share 1 HDTV. This will be shared in later logs.   

Any comments are welcome!

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