In order to let people know well and deeply about RggBer hardware and how it satisfy user’s development, we new created several separate projects in below links:

RggBer is a full open source hardware product. You may find all the necessary design resources on github site.

We set up very clear design criteria prior to the designs. RggBer must:

  1. Able to capture full color images in real time up to 1080p, 60Hz
  2. Able to receive full color digital video streams up to 1080p, 60 Hz
  3. Able to transmit full color digital video streams up to 1080p, 60 Hz
  4. Able to provide adequate bandwidth for frame buffering
  5. Extensible for future functions and formats
  6. Accessible via multiple interfaces
  7. Easy to assemble and integrate as needed
  8. Affordable
  9. Fully open in terms of documentation and source code

The top level hardware diagram shown below satisfies these criteria.


The main RggBer hardware consists of one FPGA core board and one image based board. The FPGA core-board connects to the imaging base-board via two high-speed, board-to-board connectors. It provides user I/O to the FPGA, PLL clock outputs, and dedicated global clock inputs for future expansions. The board level hardware diagram is shown below:


RggBer’s dual board design has several advantages:

  • Space savings.
  • The imaging base-board can be easily updated to support an alternative display port, 4K resolution, and other new video technology.
  • The FPGA core-board can be used for other FPGA-based projects, such as digital signal processing or multi-axis motor control.

The schematic and BOM of these two boards are open to users.

FPGA core board

Image base board
A : borad to board connector, FG : HDMI output, type CM : HDMI input, type C
B : USB2.0 and +5VH : iXCtrl interface N : SD card interface
C : FPGA JTAG interfaceI : MCU C2 interfaceO : HDMI RX chip
D : iXHis interfaceJ : MCU chipP : mini USB, +5V
E : FPGA chipK : HDMI TX chipQ : BL4.0 module
F : DDR2 chipL : borad to board connector, MR : iXCIS interface

Board to Board connectors pin definition


RggBer main chips are shown here:

FPGA28848 LEs, 594Kbs embedded memory, 66 18x18 multipliers, 4 PLLs, support DDR2 up to 200Mhz.
DDR22Gbits, 2 chips x 16bits x 64M x 400Mhz, up to 12Gbps.
MCU32K flash, (2K+256) sram, 50Mhz, 12bits ADC, 12bits DAC.
HDMI TX chipVideo only, pixel rate 165Mhz, 1080p and WUXGA at 60Hz, RGB 24bits
HDMI RX chipVideo only, pixel rate 165Mhz, 1080p and WUXGA at 60Hz, RGB 24bits
BLE4.0 moduleBluetooth to UART module


RggBer provides three I/O interfaces: iXHis, iXCIS and iXCtrl. You can use them to expand RggBer’s application support and functionality.

iXHis is the interface that supports high speed channels. It uses a 50-pin FFC connector to easily connect to a USB3.0 bridge chip, an ultra high-speed image sensor, a second channel HDMI receiver, Gige PHY chip and camera-link, etc.

iXCIS is the interface that supports a standard DVP port. Via this 24 pin FFC connector, RggBer can connect to various mainstream image sensors and ISP chips.

iXCtrl is a 10-pin FFC connector that provides basic control capabilities, such as LED control, temperature control, and other PWM based controls. This allows RggBer to work in stand-alone machine vision applications.