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8 Bit TTA Interpreter

TTA (Transport Triggered Architecture) is very simple CPU type.

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The Weird CPU is an 8 bit TTA (https://hackaday.io/project/12879-weird-cpu). It has a binary front panel, used for programming and program display. It has an 8 bit wide data bus and an 8 bit wide address bus. This limits the CPU to 128 bytes of ROM for the monitor, 120 bytes of RAM for the program. The other 8 bytes is for the embedded hardware (i.e. the ALU, PC and I/O registers). This project looks at the development of an "interpreter" for the TTA architecture.

The Weird CPU (TTA8)

Here is my 8 bit Weird CPU  (https://hackaday.io/project/12879-weird-cpu) in action (playing LED Light Chaser):

When programming, the bottom (red) LEDs are for the memory address entry, and the top (yellow) are for data entry. The extra switch on the left of the top row is the reset button.

Micro-Code and Micro-Programming

The TTA8 instruction set is very minimal:

  • Move Fetch_Address to Deposit_Address

With the Input/Output (I/O), Program Counter (PC) and ALU embedded in the address space, we also have:

  • Unconditional Jump
  • Jump On Carry
  • ADD
  • NAND
  • Input/Output

The input/output registers (REGA and REGD) are used by the Front Panel.

The TTA8 native instruction set is not very OpCode like, that is why the CPU is called Weird! The native instruction is It is best described as micro-code. And coding micro-code is often called micro-programming.

The major limitation for the TTA architecture is that the code density is very low. It takes a lot of instructions (or a lot of hardware) to do anything useful. The purpose of an interpreter is the increase the code density, to make the code look move conventional or OpCode like. The cost of this is execution speed.

The TTA8 just does not have enough memory (without paging) to develop a serious interpreter, but the code developed will run on a 16 bit TTA (TTA16) providing the architecture is similar. So it makes a good test bed to get an idea of what is possible.

Proposed Memory Mapping

Here is the basic memory map of the TTA8:

Starting from the top:

  • Hardware registers:
    • Unconditional jump
    • Jump on carry
    • Front panel data register (I/O)
    • Front panel address register (I/O)
    • ALU: Q register (write) or NAND register (read)
    • ALU: P register (write) or ADD register (read)
  • Indirect addressing (i.e. pointer move)
    • The TTA architecture uses self-modifying code for indirect addressing
  • CPU Model:
    • Instruction Pointer (IP)
    • Stack Pointer (SP)
    • Other registers (proposed)
  • Stack
  • Program constants
  • Program code (ROM)
  • Monitor code (ROM)

The Interpreter

An interpreter allows the CPU to emulate OpCodes and there by increase the code density. The cost to this is speed. An interpreter is very roughly 10 times slower than native code. Actually it is much slower because the Interpreter has other house keeping duties, such as managing the Interrupts.

Update

After many months of working on this project it is time to de-clutter.

AlanX

spreadsheet - 122.44 kB - 04/07/2019 at 13:45

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- 82.02 kB - 04/07/2019 at 13:45

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x-msvideo - 2.73 MB - 04/02/2019 at 03:35

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Adobe Portable Document Format - 2.14 MB - 03/23/2019 at 05:41

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TTA8.fd

The XForms fdesign file

- 47.27 kB - 03/19/2019 at 01:33

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  • Firmware Upgrade Completed

    agp.cooper04/07/2019 at 09:38 0 comments

    Firmware Upgrade

    The TTA8 basically does not have OpCode like typical CPUs. It has a few micro-codes that are quite limited and rather difficult to use. The Interpreter reads "OpCode" and calls a subroutine. The CPU model is also simulated.

    The "Firmware Upgrade" as mostly about adding more registers to the System area. This unfortunately changes almost all of the existing register addresses. The reason was that I need more space near the top of memory for long pointer moves (to allow for writing to FRAM).

    Anyway, its done now. More registers will be added later but they will be below the System area and will not affect much.

    Serial IO Board

    Sent away a new Serial IO Board. Swapped out the 74HC93 for a 74HC161. The 74HC93 is rather rare nowadays (even though I have two spare).

    Serial Monitor

    The next firmware upgrade will be the addition of a serial monitor.

    ZIF Sockets

    I am definitely going to make a new programmer and Paged Memory Board with a ZIF sockets. I don't know why I have not done this so far. I suppose I never expected to need to reprogram the chips so many times.

    AlanX

  • Adding the Serial Card

    agp.cooper04/03/2019 at 01:02 0 comments

    The Serial Card

    Well now I am getting excited! Okay not that excited as he chances of it working first time are practically zero. This card is complex and it is my first attempt at a serial design. What could go wrong!

    Here is the design:

     That big red line is a jumper I had to add as I forgot to craw it in the schematic and the PCB.

    Rereading the Schematic or What Did I Design!

    • U1-U5 decodes REGA and REGD and uses IO address 7 to read/write the serial data.
    • U6-U13 is the serial circuity.
    • U10.1 triggers INTR6 t0 indicates a byte has been received, and reset upon a read of the serial data.
    • U10.2 trigger the "serial in" clock on the "start bit".
    • Currently the serial interface is TTL but a current loop would be more "authentic".

     Okay, ready to code and "echo" program.

    No Surprise!

    Not surprised its not working. Working through the code:

    • MASK works
    • INTR works
    • ISR works
    • the Serial Card is holding INTR6 high?

    Ah yes, I have to do a dummy read to clear INTR6. It should have been cleared on RESET/CLR.

    Also I am not sure what happens on boot up  and clock reset.

    TXD in is indeterminate if disconnected.

    Need to add some RESET/CLR logic to the schematic.

    Not sure how Serial Out gets the clock signal? I have hooked it up to the Serial In clock that is triggered by the start bit.

    I think I may need to rework the schematic NOW.

    More Problems

    INTR6 can be reset by reading the serial data port. But better if it does not trigger on start up.

    The RX and TX signals have been swapped.

    And a 20ns glitch between the two 74HC165:

    The glitches are between D6, D7 and the two Marks. The data is "85" so D7 is wrong.

    D6, D7 and the Marks come from the second 74HC165 via QH and SER (serial in).

    I am puzzled by the glitches and D7 as the part of the schematic is a rather simple design.

    ---

    I ran with a different Interpreted program and get a different pattern.

    Yeah, I am writing new data at the baud rate (2.4kHz) rather than 1/10 or 1/11 of the baud rate.

    Need to add a dedicated counter to the Timer Interrupt.

    Success

    Well at least the the first test. Need to do a bit more to prove it (later as I have other chores to do today).

    • The test write 85 (i.e. 01010101 once every 12 timer interrupts (INTR7) to the serial port.
    • The test data (i.e. 85) is written to the ADDR LEDs.
    • The TXD is linked to RXD.
    • If INTR6 fires then the serial port is read (resetting INTR6).
    • The read data is written to the DATA LEDs.

    Okay a better test would be to write data to the ADDR and the show the read data on the DATA LEDs. I will do that later before ording a new Serial IO PCB Board.

    ---

    Time for a system rewrite, I need to make room for extra system variables (Serial Data, Timer Counter, etc), and provision for inter-page read/write. Here is the new system:

    Its getting complicated and I have to write notes on its use:

    I also want to shuffle the ROM pages around so that I can user the Monitor Run Program command to select a ROM page to run.

    ---

    Anyway, I have created a new Serial IO PCB board but I have to check on the availability or my stock of the 74HC93. Its pretty rare now so I should substitute.

    ---

    Really cool! Wrote some code to echo Serial In to Serial Out and to display the data on the front panel. Really cool after opening Putty to type stuff in the terminal to see the TTA8 echo it back and the front panel to display the character binary code (received and sent).

    So final checks on the replacement Serial IO Board before sending off for manufacture.

    AlanX

  • Adding the Interrupt Board

    agp.cooper04/02/2019 at 09:13 0 comments

    The Interrupt Board

    The Interrupt Board has three functions:

    1. read the interrupt inputs
    2. trigger an INTR7 every 417us (=2.4kHz)
    3. and provide the serial clock (SCLK=38.4kHz).

    Notes:

    • INTR7 is used as a timer.
    • INTR6 is the Serial In interrupt.
    • Interrupts are read every time the Interpreter is called.
    • Reading the interrupt register clears the interrupts so they are stored in "INTR".

    Interrupt Programming

    Recoded the Interpreter to call (if there are any interrupts) one ISR after another. Its up to the ISR to check if the interrupt is for it.

    As a test to check that the interrupts are actually being called, I wrote a short interpreted infinite loop. Then coded ISR7 to do a 16 bit binary count.

    Pretty cool actually. The concern is that interpreted code is much slower than expected and the interrupts timing is perhaps too fast. Roughly five interpreted OpCodes per interrupt.

    I may look at redesigning the interrupt card to slow it down.

    Otherwise good progress.

    AlanX

  • IC5 on the Control Board has retired!

    agp.cooper03/25/2019 at 01:53 2 comments

    Celebrated Too Soon

    After glowing with the success of getting the machine working, I modified the monitor and it stopped working! After a day of mucking around with monitor code, I thought I better check if the signals are working. Checked with the oscilloscope and they appeared to be there. Checked the address/data bus and it was not reading the FRAM correctly. Replaced the FRAM (no), cleaned the boards (no). Okay check the signals properly (yes), the Control Board is not working properly. I have blown up IC5? How?

    I will have to wait until the new boards arrive.

    16 bit counter demo code

    The new code has a 16 bit counter that will visually look better. I will post a video to prove that the machine is working!

    Next Steps

    Lot of things that could be done but writing some code to "save" and "load" a RAM page to FRAM sound like a good idea. Save recoding after each power up.

    After that setting up the Serial IO interrupt code seems like a nice (big) step.

    ---

    Saving code to FRAM is a bit tricky as FRAM is not available while being programmed.

    So I need to load a program into "static" memory (0xC0 to 0xDF), not much to play with.

    It is possible to swap between RAM pages, if necessary.

    Anyway so I wrote some code to load from FRAM to RAM (0x80 to 0xBF), and auto-execute. At least I don't have to toggle code into the front panel anymore (other than than the six byte to load the code).

    ---

    Uploaded the latest emulator code.

    ---

    Replace the Control Board. No success.

    The Paged Memory Board is reading rubbish but the FRAM read/write okay.

    So I will have replace this board as well.

    I am really surprised I destroyed two board with protective capacitors across every chip.

    It was not like I noticed a static discharge.

    Checked the ALU Board and it seems fine.

    Don't have a check for the PC Board.

    ---

    Refreshed my memory with the inner workings of the Interpreter.

    Wrote a number of OpCodes:

    • _Delay(ms)
    • Mov AX,[BX] (current ROM/RAM Page only)
    • Mov [BX],AX (current RAM Page only)
    • Push AX
    • Push Bx
    • Pop AX
    • Pop BX
    • Xchg AX,BX
    • Xchg AX,CX
    • Xchg AX,DX
    ---

    Replaced the Paged Memory Board. All good the CPU is talking to me now.

    Used the front panel to input a 16 bit counter. Works fine.

    ---

    Although I coded ROM Page 6 with a loadable 16 bit counter I could not get it to work?

    It works on the emulator though.  Perhaps the FRAM does not have the latest code?

    ---

    The problem was that the Arduino Code was only set up to write 8 pages (4 ROM pages).

    I am up to ROM page 6! So easy fix. And guess what, the program load code works.

    All Good!

    AlanX 

  • Coding Errors

    agp.cooper03/19/2019 at 14:22 0 comments

    Coding Errors

    I seem to have been a bit careless keeping the most up to date monitor code.

    Whilst the emulator code is correct, the copy of the spreadsheet is not.

    I have mixed the address of the ROM Page and the RAM Page.

    The Flash Code is correct for Page 0, Page 2 and Page 3 but not Page 1 (but I have not got that far).

    Going though the Logic Analyser data I am getting incorrect reads (i.e. not equal to the Flash Code). This means:

    • I should look at slowing the clock down, and
    • improving the bus.

    Easy to check, I have a new Control card without the crystal installed.

    I can clock the CPU at 1kHz and see if it works.

    Improving the Bus

    I think this is really called bus terminations. Looking at the options I think I can add a card at the end of the mother board with something like the Bourns' RC termination (https://www.bourns.com/pdfs/rctermap.pdf):

    The values are:

    The typical bus impedance is in the order of 50 ohms.

    I designed the Bus Termination Board but before getting it made I thought I would look at the CPU signal on the oscilloscope. Now you may ask why not before, the reason is that it is quite hard to work out what you are looking at. Anyway I thought I knew what I was looking for now.

    Well I found no evidence of ring,all good except the data bus:

    Okay, the blue trace is the REGS signal (low is reading/writing to a register), the yellow trace is the data bus. Very sharp signals except for second last yellow pulse. This is very likely from the FRAM. The signal is delayed about 80 ns, not surprising as the FRAM is rated as 90 ns! Now the write pulse would be rising around the 100 ns mark, very close for comfort! Here is another:

    This time the FRAM is clearly too late. So okay, the problem appears to be a FRAM that is just too slow. So to test I need to lower the clock frequency.
    ---

    Found a 2.4576MHz crystal, added to the updated PCB I had made and assembled.

    Plugged it in and no! Checked the logic analyzer and the signals are wrong, what!

    Okay, logged on the EasyEDA and checked the schematic and PCB, checks out okay (according to the design manager). "RD" is not working so checked the schematic, looks okay. Checked the PCB and "VCC" is connected to "RD". That's not right. Unrouted the PCB and reran the router, same error. Log a bug report, may need to find another PCB supplier as you cannot afford this types or errors. But I will see what they say.

    Spent the morning tracking the error, back to the schematic and to U5.3 pin 4.

    Here is the PCB error (VCC connected to RD, at the bottom):

    Here is the Schematic:

    Notice U5.3 should be U6.3! The problem is that pin 4 to U5.3 is connected to pin 4 for U5.2 which is linked to VCC! So my fault when I renumbered the ICs.

    Ordered a new control board and the bus termination board.

    Partial Success

    The code advances past the key check before failing. That means the jump to ROM Page 1 works. I checked the emulator and I was getting write to ROM in this area. The fault was "NOP", I had coded this as read/write address 0x00, a ROM address. A write to FRAM will cause write cycle but will not actually write the data. Not good as this means the FRAM will stop responding to normal reads. So I recoded "NOP" as read/write to 0xEF, the TEMP variable in RAM.

    So it boots up and allow me to read/write memory. The debounce does not seem to be working but I persisted and coded my binary counter. It works! Clocking LED D7 at about 7 Hz.

    It also does not boot properly on power up (the reset on the old control board?). But a manual reset works.

    So A good morning's work. Need to look at the Reset circuity and the monitor debounce code....

    Read more »

  • Port TTA8 EMU to XForms

    agp.cooper03/18/2019 at 06:55 0 comments

    TTA8 Status

    The machine is waiting for me to check why the latest card (Program Counter Board) did not work.

    But I thought I would port my old TTA8 EMU code to XForms. Not that easy as there are lots of buttons and labels to design and code. Here is current the form:

    I have hidden the file management buttons.

    These GUI programs get very big very quickly, in total 1200 lines of code so far.

    Speed wise it is slower than the original version and the output screen is a bit jerky when running fast, but it works fine.

    The built in "user" code is a binary counter, using the interpreter. The interpreted instructions are: Call, Jmp, Inline (i.e. native micro-code) and Rtn:

    Now that I have written a compiler that is suitable for this machine, so I now have the PCodes I need to "micro-code" for the interpreter (if that makes sense!).

    Its all a tight fit for an 8 bit CPU with an 8 bit address space (even with paging).

    For the "shell" I an considering my cut down version of "Mouse" with the ability to call ROM programs.

    But need to get the machine working first.

    I have uploaded the EMU_GUI project.

    AlanX

  • Almost Working

    agp.cooper03/04/2019 at 23:24 0 comments

    Almost Working

    Updated and tested the Software Data Protection version on the FRAM programmer.

    I had set my self a trap! "A14" is not set using SetAddr(), It has its own routine. But it is working now. I have uploaded the code.

    Endless Loop

    I also wrote a Control Card simulation so I could test the bus. Surprisingly the CPU is mostly working before going into an endless loop.

    It fails when I try to change the ROM Page. It should wait until a jump before changing the Page but it changes the Page immediately.

    It seems as if the LOAD signal (which signals the PC to jump on the next clock) is glitched.

    Using the logic analyzer I did (once) get it to show glitches every write machine cycle.

    How to fix?

    Cross-talk on the CLR Signal

    I am getting about 5 clock cycles on the CLR signal as the Reset triggers reset schmitt trigger. It does not appear to affect (but there is some evidence that it does!) the control circuit. It could be internal cross-talk (as the clock and reset circuity share the same chip) or external cross-talk because the components are close together.

    I am thinking of adding a 47 pF capacitor to the input gate of the reset logic.

    Next time I will use a 74HC14 rather than build my own Schmitt trigger.

    ---

    The capacitors did not work.

    Redesigned the clock and reset circuity.

    Redesigned the load signal to avoid the glitch areas between the machine cycles.

    Redesigned the boards and sent them off to be made.

    Bugger no sooner than I sent the order off I found an error.

    Oh well, I will sent the updated board tomorrow.

    I am getting close to working!

    AlanX 

  • Debugging

    agp.cooper02/01/2019 at 06:33 0 comments

    Debugging

    Need to get this project working.

    One problem is that the Nano does not have enough pins.

    So I have used a Meduino (a Mega2560 Pro Mini).

    Here is the schematic:

    Here is the PCB:

    The ports (P1 & P2) match the TTA8 bus.

    A problem with the Meduino is that pins do not align with the ports (unlike the  Nano).

    So it is awkward to go fast. Awkward just means more coding. But do I really need to go fast? This time I have coded using pinMode, digitalRead and digitalWrite.

    Here is the Mother Board I/O test code:

    /*
      Front Panel Board Test
      ======================
    REGISTERS:
      Hex  Address Write   Read      Comment
      FF   255     JMP     INTR      Jump/Intr
      FE   254     JC      Reserved  Jump on Carry
      FD   253     ROM     Reserved  ROM PAGE
      FC   252     RAM     Reserved  RAM PAGE
      FB   251     REGD    REGD      DATA REG
      FA   250     REGA    REGA      DATA REG ADDR
      F9   249     REGQ    NAND      ALU
      F8   248     REGP    ADD       ALU
      
    SYSTEM (Pointer to Pointer Copy):
      Hex  Address Write   Read      Comment
      F7   247     JUMP    JUMP
      F6   246     POINTER POINTER 
      F5   245     DEPOSIT DEPOSIT 
      F4   244     FETCH   FETCH 
      F3   243     DATA    DATA      
      F2   242     ADDR    ADDR      
      F1   241     RETURN  RETURN  
      F0   240     PAGE    PAGE  
      
    CPU MODEL:
      Hex  Address Write   Read      Comment
      EF   239     TEMP    TEMP      
      EE   238     DELAY   DELAY     
      ED   237     INTR    INTR      
      EC   236     MASK    MASK      
      EB   235     PP      PP        Page Pointer
      EA   234     IP      IP        Instruction Pointer
      E9   233     SP      SP        Return Stack Pointer
      E8   232     DX      DX        (Monitor Data I/O)
      E7   231     CX      CX        (Monitor Addr I/O)
      E6   230     BX      BX  
      E5   229     AX      AX  
      E4   228     TX      TX        Temp Register
      E3   STACK
      E2   STACK
      E1   STACK
      E0   STACK
      ...
    
      0xF8-0xFF REGISTERS  (8 registers)
      0xC0-0xF7 STATIC RAM (56 bytes at page 0xFF)
      0x80-0xBF PAGED RAM  (64 bytes)
      0x00-0x7F PAGED ROM  (128 bytes)
        
      CPU Emulation:
        This CPU has no actual opcodes.
        All instructions are MOVE from [PC] to [PC+1]
        i.e. Move DATA from source ADDRess to destination ADDRess.
    
        The 4 cycles are:
        1 Fetch the destination ADDRess pointed to by the program counter and put in the ADDR register
        2 Fetch destination DATA pointed to by the ADDR register and put and the DATA register
        2A  Increment the program counter (PC)
        3 Fetch destination ADDRess pointed to by the program counter and put in the ADDR register
        4 Deposit the DATA register into the destination pointed to by the ADDR register
        4A  Increment the program counter (PC)
    
        All hardware (PC,IO and ALU) is memory mapped.
    */    
    
    // Board Connections:
    //       Bus       Meduino Pin
    //       VCC 
    //       GND       Gnd
    #define  RST       2
    #define  CLR       3
    #define  PC_OUT    4
    #define  PC_CLK    5
    #define  ADDR_OUT  6
    #define  ADDR_CLK  7
    #define  DATA_OUT  8
    #define  DATA_CLK  9
    #define  RD        10
    #define  WR        11
    #define  REGS      12
    #define  CARRY     13
    #define  LOAD      14
    #define  SCLK      15
    #define  Data0     16
    #define  Data1     17
    #define  Data2     18
    #define  Data3     19
    #define  Data4     20
    #define  Data5     21
    #define  Data6     22
    #define  Data7     23
    #define  Addr0     24
    #define  Addr1     25
    #define  Addr2     26
    #define  Addr3     27
    #define  Addr4     28
    #define  Addr5     29
    #define  Addr6     30
    #define  Addr7     31
    #define  Intr0     32
    #define  Intr1     33
    #define  Intr2     34
    #define  Intr3     35
    #define  Intr4     36
    #define  Intr5     37
    #define  Intr6     38
    #define  Spare     39
    
    void InitialiseBoard(void)
    { // Reset State
      pinMode(RST,INPUT_PULLUP);   // Dont care 
      pinMode(CLR,OUTPUT);         digitalWrite(CLR,LOW);
      pinMode(PC_OUT,OUTPUT);      digitalWrite(PC_OUT,LOW);
      pinMode(PC_CLK,OUTPUT);      digitalWrite(PC_CLK,LOW);
      pinMode(ADDR_OUT,OUTPUT);    digitalWrite(ADDR_OUT,HIGH);
      pinMode(ADDR_CLK,OUTPUT);    digitalWrite(ADDR_CLK,LOW);
      pinMode(DATA_OUT,OUTPUT);    digitalWrite(DATA_OUT,HIGH);
      pinMode(DATA_CLK,OUTPUT);    digitalWrite(DATA_CLK,LOW);
      pinMode(RD,OUTPUT);          digitalWrite(RD,HIGH);
      pinMode(WR,OUTPUT);          digitalWrite(WR,HIGH);
      pinMode(REGS,OUTPUT);        digitalWrite(REGS,HIGH);
      pinMode(CARRY,OUTPUT);       digitalWrite(CARRY,LOW);
      pinMode(LOAD,OUTPUT);        digitalWrite(LOAD,HIGH);
      pinMode(SCLK,OUTPUT);        digitalWrite(SCLK,HIGH);
      pinMode(Data0,INPUT_PULLUP);
      pinMode(Data1,INPUT_PULLUP);
      pinMode(Data2,INPUT_PULLUP);
     pinMode(Data3,INPUT_PULLUP);
    ...
    Read more »

  • Assembled Paged Memory and Interrupt Boards

    agp.cooper08/17/2018 at 06:41 0 comments

    Assembled the Last Two Boards

    I will skip the board testing and will code the Monitor to the FlashROM (AT29C256).

    You never know I may get lucky.

    I designed and build a Nano controlled FlashROM programmer a while back:

    Programmer Failure?

    I loaded the AT29C256 chip into the stripboard version of my Flash ROM programmer, uploaded my code but it did not work (i.e. load). Stripboard sometimes needs to be cleaned if it has been sitting around for a while. Still no. Found the PCB version of the programmer and still no? Salvaged a known good chip and the programmer was fine. Another bad AT29C256 chip! I have had a few bad chips so I was sort of expecting it.

    Loaded the chip into the Page Memory board and no. So I need to test the board.

    AlanX

  • Mother Board Tested

    agp.cooper07/27/2018 at 08:36 0 comments

    Mother Board Tested

    Okay, finally got around to assembling and testing the lastest Mother Board.

    All good. Uploaded the Arduino sketch (TTA8_IO_TestWorking.ino) that I used.

    ---

    I have been busy following the Australian "My Healt Record" debacle. It is just amazing how bad politicians lie and how little regard they have for the public.

    ---

    I have more boards that need to be assembled and tested.

    ALU Board Tested

    You can add the ALU board to the pass list.

    The Timing Board passed the logic analyser test previously.

    I have double checked the Program Counter Board but it's hard to test so it passed for the moment.

    I will assemble the Timer/Interrupt Board next.

    Ordered some 74HC273 chips. Should arrive by friday. After that I can assemble and test the Paged ROM/RAM Memory Board. The ROM code is ready, just need to set up the programmer.

    I have assembled a Serial I/O Board but testing can wait.

    AlanX

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