So now that I have enough modules assembled to do some testing, I programmed the ROM with a series of test patterns to exercise the program counter, the OP Code Register, and the Immediate Data Register. The first 16 bytes of the ROM are programmed with 0 to F in the upper nibble which corresponds to the OP Code. The second set of 16 bytes of the ROM are programmed with 0 to F in the lower nibble which corresponds to the Immediate Data. The third set of 16 bytes, have both the OP Code nibble and the Immediate Data nibble programmed from 0 to F. This pattern helps identify any LSB/MSB signal swaps as well as make sure the ROM is reporting data from the correct address. In this video, I run the test first at 2Hz clock, reset the board, and then run at the 10Hz clock. At the end of the video, I demonstrate using the "step" button to pulse the system clock. So far things are looking good!