Before I began the layout of the DDL4-CPU, I came up with an initial Instruction Set Architecture (ISA) for the design. It went through several revisions as I was designing the boards and refined the components. Here at the last minute as I am programming the EEPROMs, I decided to make a few last minute changes. I am using a 4-bit opcode with a 4-bit immediate. I've also allowed for in the design to have 2-byte commands. I only plan to implement the 2-byte commands with the conditional jump commands with this revision. This is mainly to work out the details of how it should work. It was a challenge to come up with an optimal configuration. I reviewed a lot of third party designs including the TD4 cpu described in the Japanese language book "How to Build a CPU" by Iku Watanabe. A good English description of the book and contents can be found at the "Building a 4-Bit CPU" web page. You can also find a number of attempts at building a TD4 cpu on hackaday.io pages!