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Microassembler and Fetch Test

A project log for BREDSAC

Electronic Dynamic Storage Breadboard Computer

greg.ewinggreg.ewing 06/14/2018 at 11:460 Comments

I wrote a simple assembler in Python for the microcode.

Here's what the microcode for fetching an instruction looks like:

AddressBits = 10
DataBits = 15

# OPCODE D STAT : FETCH MASEL SHS

# Fetch
   xxxxx x 0000 :   1     0    1

Lines beginning with # are comments. After a header indicating how many address and data bits to expect, there are lines containing an address and some data bits separated by a colon. The data bits are in reverse order, with bit 0 on the left; I did that so I could add more microinstruction bits easily without having to reformat things. Any unspecified high-order data bits are padded with 0.

The 'x' characters in the address are don't-care bits. The reason for them is that I'm planning to use a trick that Ben Eater used in his breadboard computer, and repeat the instruction-fetching microcode at the beginning of the microcode for every instruction. When the microassembler sees don't-care bits in an address, it fills in all matching address combinations with the same data.

The output of the microassembler is a file suitable for loading into a Logisim memory component.

Instruction Fetch Test Video

Here's a video showing the above microcode being tested in Logisim.

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