- Adder - See Full Adder and Half Adder.
- AND Gate - A gate who's output is 1 only when all inputs are 1.
- Blocking assignment - In Verilog, when an assignment occurs before any subsequent assignments (that is, it does not occur in parallel).
- Combinatorial Logic - Logic that does not rely on the previous state of the system to set the current output state.
- Exclusive OR Gate - See XOR Gate.
- Flip Flop - A circuit element that can take one of two states (1 or 0) and remember it until changed. Somewhat like a one-bit memory device.
- Full Adder - A circuit for adding two binary numbers and a carry bit (so three bits overall). It will produce a sum and a carry.
- FPGA - Field Programmable Gate Array.
- Half Adder - A circuit for adding two binary numbers. It will produce a sum and a carry
- Inverter - See NOT Gate.
- IP - Intellectual Property. Typically a third party module that does a particular function that you can integrate into your FPGA designs if you wish.
- Logic Diagram - See Schematic.
- Non-blocking Assignment - In Verilog, when an assignment occurs in parallel with other assignments in the same block.
- NOT Gate - A gate that takes a single input and inverts it. That is, a 1 becomes a 0 and a 0 becomes a 1.
- OR Gate - A gate who's output is a 1 if any inputs are 1.
- Schematic - A diagram of a logic circuit made up, usually, of logic symbols for fundamental gates.
- Sequential Logic - Logic that typically uses flip flops and the current output state influences future output states.
- Testbench - Verilog (or similar) code that exists only to send stimulus to a simulated device and record or test the results.
- Truth Table - A table showing a logic circuit's possible inputs and the outputs that will result.
- Workflow - The process of taking design inputs and producing a working FPGA configuration.
- Verilog - A description language used to describe logic you wish to place on an FPGA.
- VHDL - A description language (not used in this bootcamp) to describe logic you wish to place on an FPGA.
- XOR Gate - Exclusive OR gate. A two-input gate that sets its output to 1 if either input is a 1, but not when both inputs are a 1.

Logic Truth Tables for Two-Input Gates

A | B | AND | OR | XOR |

0 | 0 | 0 | 0 | 0 |

0 | 1 | 0 | 1 | 1 |

1 | 0 | 0 | 1 | 1 |

1 | 1 | 1 | 1 | 0 |

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