DTTL LUT.txtA lookup table made with transistors.plain - 2.59 kB - 07/01/2018 at 04:13 |
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DTTL inverters.txtusing both an NPN and PNP transistor for logic outputplain - 2.26 kB - 07/01/2018 at 04:13 |
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DTTL double LUT clock.txtTwo LUTS configured as one inverter and one buffer, connected to produce a clock signal.plain - 6.35 kB - 07/01/2018 at 04:13 |
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DTTL NAND.txtNAND gate with both NPN and PNP transistors for logic outputplain - 1.61 kB - 07/01/2018 at 04:13 |
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DML logic family.txtdiode-MOSFET-logic family (insted of DTL)plain - 2.02 kB - 07/01/2018 at 04:13 |
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