07/12/2018 at 20:46 •
If you start with a C program, you use a compiler and a linker to convert that code into an executable format. You might use one toolchain to generate a Linux executable and another for a Windows EXE. Still another might produce a hex file to put in an Atmel processor. Even though each takes different tools, the process is more or less the same and it is an analog for how we configure an FPGA.
Whatever tools you use, the workflow for any FPGA is basically the same, although details of the specific tools may vary. Sometimes the names vary a bit, too. Although you write code in Verilog, the FPGA has different blocks (not all vendors call them blocks) that have certain functions and methods they can connect. Not all blocks have to be the same either. For example, some FPGAs have blocks that are essentially look up tables. Suppose you have a look up table with one bit of output and 16 rows. That table could generate any combinatorial logic with 4 inputs and one output. Other blocks on the same FPGA might be set up to be used as memory, DSP calculations, or even clock generation.
Some FPGAs use cells based on multiplexers instead of look up tables, and most combine some combinatorial logic with a configurable flip flop of some kind. The good news is that unless you are trying to squeeze every bit of performance out of an FPGA, you probably don’t care about any of this. You write Verilog and the tools create a bitstream that you download into the FPGA or a configuration device (more on that in a minute).
The general steps to any FPGA development (assuming you’ve already written the Verilog) are:
- Synthesize – convert Verilog into a simplified logic circuit
- Map – Identify parts of the synthesized design and map them to the blocks inside the FPGA
- Place – Allocate specific blocks inside the FPGA for the design
- Route – Make the connections between blocks required to form the circuits
- Configure – Send the bitstream to either the FPGA or a configuration device
The place and route step is usually done as one step, because it is like autorouting a PC board. The router may have to move things around to get an efficient routing. Advanced FPGA designers may give hints to the different tools, but for most simple projects, the tools do fine. Synthesize and map are often done in one swoop, also.
One way to think of this is that someone has given you a printed circuit board with a bunch of components holes already drilled out but all the copper is still on it. So you know a resistor is going to go in these holes and an IC in another set of holes. You can't change that. The synthesize and map steps take your design and figure out how to implement it with the components that are there. Like a schematic, though, that doesn't tell you anything about a component's position on the board or any traces. The board might have 10 resistors and you need 3. The schematic doesn't tell you which 3 you are going to use.
The place and route steps then take that schematic and determine which components you will make use of and how to etch the copper to form the traces between them. To carry the analogy further, the configuration step is the etching and building of the board.
Of course, there's no copper and etching involved. That's just an analogy. We'll talk about constraints which can tell the place and route steps that you insist on using a certain component for a certain Verilog construct. That's important when you have, say, a particular I/O pin connected to something and you need a signal to drive it, although there are other reasons you might do it, as well.
Even though we are talking about a very specific board in this bootcamp, you'll find that if you are using Verilog to configure an FPGA the steps will always be pretty close to this. Some tools will have slightly different names or break the tasks up differently, but all of these tasks will still apply.
Another common way to configure an FPGA is with VHDL which is another description language. The workflow is very similar for that, also except you'll use different tools.
There are other tools people use to configure FPGAs. Sometimes they will allow you to create configurations using a subset of a common language like C. Or you'll find graphical tools that let you pick predefined function blocks and compose them to make -- essentially -- a custom CPU. While these steps won't be happening visibly, they still occur somewhere under the covers.
07/12/2018 at 19:49 •
- Adder - See Full Adder and Half Adder.
- AND Gate - A gate who's output is 1 only when all inputs are 1.
- Blocking assignment - In Verilog, when an assignment occurs before any subsequent assignments (that is, it does not occur in parallel).
- Combinatorial Logic - Logic that does not rely on the previous state of the system to set the current output state.
- Exclusive OR Gate - See XOR Gate.
- Flip Flop - A circuit element that can take one of two states (1 or 0) and remember it until changed. Somewhat like a one-bit memory device.
- Full Adder - A circuit for adding two binary numbers and a carry bit (so three bits overall). It will produce a sum and a carry.
- FPGA - Field Programmable Gate Array.
- Half Adder - A circuit for adding two binary numbers. It will produce a sum and a carry
- Inverter - See NOT Gate.
- IP - Intellectual Property. Typically a third party module that does a particular function that you can integrate into your FPGA designs if you wish.
- Logic Diagram - See Schematic.
- Non-blocking Assignment - In Verilog, when an assignment occurs in parallel with other assignments in the same block.
- NOT Gate - A gate that takes a single input and inverts it. That is, a 1 becomes a 0 and a 0 becomes a 1.
- OR Gate - A gate who's output is a 1 if any inputs are 1.
- Schematic - A diagram of a logic circuit made up, usually, of logic symbols for fundamental gates.
- Sequential Logic - Logic that typically uses flip flops and the current output state influences future output states.
- Testbench - Verilog (or similar) code that exists only to send stimulus to a simulated device and record or test the results.
- Truth Table - A table showing a logic circuit's possible inputs and the outputs that will result.
- Workflow - The process of taking design inputs and producing a working FPGA configuration.
- Verilog - A description language used to describe logic you wish to place on an FPGA.
- VHDL - A description language (not used in this bootcamp) to describe logic you wish to place on an FPGA.
- XOR Gate - Exclusive OR gate. A two-input gate that sets its output to 1 if either input is a 1, but not when both inputs are a 1.
Logic Truth Tables for Two-Input Gates
A B AND OR XOR 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 1 1 1 1 0