Instruction set ideas

A project log for IO881

An I/O Processor for 8-bit systems

JulianJulian 08/31/2018 at 07:490 Comments

Have sketched out a few ideas of useful programs to run, and used them to decide on a basic instruction set architecture.  I'm still experimenting and optimising, but my basic plan at the moment is:

Register set

Current plan is for each independent thread to have the following set of registers:

Instruction packing

Instructions are loaded from an 8-bit wide SRAM.  There are three instruction formats:

Two 4-bit instructions may be packed into a single byte.  An 8-bit instruction may either be aligned to the start of a byte, or it can be packed into the spare location after a 4-bit instruction in which case all bits of its second nibble are assumed to be zero.  Jump destinations must be byte aligned.  Packing is big-endian (i.e. the first instruction executed is in the most significant nibble).

This means that the valid instructions for the second slot in a byte are the usual 4 bit instructions, NOP (1000), MOV P0L, A (1001), EXT R,1 (1010), JMP PC-1 (1011), ADD P0, A (1100), DLDB [P0] (1101), PUT #n, A (1110) and ADD rr, i6.

Some instructions (with mnemonics IFxxx) are effectively prefixes that control conditional execution of the following instruction.  An advanced implementation could fuse these to operate in a single cycle, but I'm not going to do that for now (I may support it in a CPLD/FPGA version later, but it would be too complex for the low integration logic I'm planning to use here).

Allowing 4-bit instructions makes the decoder design slightly harder, but the hope is that by packing more instructions per byte it should be possible to approach 1 instruction per clock cycle (as decode and execution will have to contend for access to the SRAM in many cases, and 2-byte instructions will of course always need 2 cycles to fetch).  A small queue (probably 4 instructions) will be used to prefetch instructions to even out delays. 

Instruction format

Bitfield identifiers:

Mnemonic notes:

OpcodeExt bitsOp byteMnemonic
Pull instructions - suspend thread until a byte is passed to the channel through the input FIFO
0000--PULL A
0001--PULL B
0010--XCHG A,B
0011--DLDB [P1+]
Yield instructions - pass a byte to the current thread's default destination (may suspend the thread until the destination is available)
0100--YIELD A
0101--YIELD B
0110--LDB A, [P0+]
0111--STB [P0+], A
1000pppp-xxx A, B
1001rrbs-MOV rrb, s
Extract operation: shift B register by n (= i+1) bits, and set the A register to the bits that were shifted out (aligned to least significant bit)
1010diii-EXT d,n
1011iiii-JMP PC-(i4+1)
110000rr-ADD rr, A
110001rr-SUB rr, A
110010rr-IFNZ rr <INSN>
1100110s-IFNZ s
1100111s-IFZ s
1101rrww-DLDw [rr]
1110000siiii iiiiPUT #n, s
to do - explanation
11100010iiii iiiiJMP i8<<4
11100011?no operation assigned
1110010siiii iiiiLDB s, [i8]
1110011siiii iiiiSTB [i8], s
1110100siiii iiiiXLAT s, [i8<<4]
1110101siiii iiiiMOV s, i8
1110110srrii iiiiLDB s, [rr + i6]
1110111srrii iiiiSTB [rr + i6], s
111100oorrii iiiiop rr, i6
111101oosiii iiiiop s, i7
1111100dsiii jjjjSdA s, i, j  [s = (s shd i) + j]
11111010pppp rrqq
xxx rr, qq
11111011rrsi iiiiDSTB [rr+i5], s
11111100iiii iiiiSCSB i8
11111101rrii iiiiSTART #i6, [rr]
11111110ncii iiiiIFxxx #i6
11111111?no operation assigned

Note that there are no CALL or RET instructions - brief analysis of use cases has suggested that they are not likely to be required. Most operations are small and simple, and in any case will usually require speed so inlining subroutines would probably be a good idea in any case.  With any luck, the 4KiB memory available to code for a channel should provide enough space for any reasonable operation.

There are two unassigned opcodes still available, but no currently foreseen applications for them. 1111_1111 seems a good candidate for extension to 3 byte opcodes, as it would be easy to detect in the prefetch circuit, so will be reserved for this purpose.

74181 mnemonics

We use an abbreviated selection of 16 useful operations out of the 32 available from the 74181.

Opcode74181 opcode & descriptionMnemonic
000000000 Q=ANOP
000101001 Q=A+BADD
001000110 (carry in high) Q=A-BSUB
00110100 Q=A+(A&B)ADA
010001111 Q=A-1DEC
010111001 Q=~(A^B)NXOR
011010011 Q=0ZERO
011111100 Q=-1MNSO
100010000 Q=~ANOT
100110001 Q=~(A|B)NOR
101010100 Q=~(A&B)NAN
101110101 Q=~BNOTB
110010110 Q=A^BXOR
110111010 Q=BCPB
111011011 Q=A&BAND
111111110 Q=A|BOR