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FPGA Board Hack

Upcycling - reuse (discarded objects or material) in such a way as to create a product of a higher quality or value than the original.

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TODO:

  1. Cisco HWIC-3G-CDMA.(EP2C35F484C8) 5-10$

    2. https://github.com/MorriganR/c2hwic

  2. Cisco VWIC3-2MFT-T1/E1 (EP2S30F484C5N) 10-15$

    3. VWIC3-1MFT (EP2S15)

  3. NVIDIA PNY VCQFXSDIOPT2 (EP2SGX30CF780CSN) 15-20$

    4. SDI in/out, DVI in

  4. MM5453CN1G Micro Memory NVRAM 1GB (XC5VLX30T) 10-15$

    5. .

  5. HP 512MB FLASH BACKED WRITE CACHE (EP3C10F256C7N) 4$

    6. JTAG pinout:

  6. Comtech AHA AHA363PCIE0301G (Altera Arria GX) 10$

    7. .

  7. IBM BladeCenter KVM Feature Card 13N0842 (EP1C12F256I7) 5-10$

    8. RU http://www.nedopc.org/forum/viewtopic.php?f=68&t=18524

  8. Dell S2716DGR, etc (Altera Arria V GX 5AGXMA3D4F...) 35-55$

    9. eBay

    JTAG pinout:

  9. Napatech NT20X (xc4vfx100) 5-10$

    10. RU https://electronix.ru/forum/index.php?showtopic=137808

  • Cisco HWIC/EHWIC/VWIC Breakout Board

    MorriganR • 11/19/2019 at 19:24 • 4 comments

    In this log there will be some of the previous versions of Breakout Boards for Cisco HWIC.

    Version 1. The cheapest.

    Version 2. More complicated.

  • Stratix II - Cisco VWIC3-2MFT

    Occamlab • 04/12/2019 at 17:24 • 0 comments

    FPGA Device

    • Stratix II GX EP2S30F484C5N Device
    • 30K Programmable Logic Elements
    • M4K RAM blocks (128×36 bits) - 144
    • M-RAM blocks (4K×144 bits) - 1

    Configuration and Debug

    • JTAG - ??

    Memory

    • Samsung K7A803600B-PC16

    Switches, Buttons, LED, and 7-Segments

    • 4 LEDs on RG-45

    Power

    • 5V DC input

    Limitations

    • Quartus II Web Edition - 11.0sp1 -- ATTENTION. There is no complete certainty!
    • Quartus II Subscription Edition - 13.0sp1

    Block Diagram

    qq

    X1_pinout <-- !!! This file contains significant inaccuracies !!!

    RAM_pinout

  • Stratix II GX SDI board

    Occamlab • 04/10/2019 at 07:35 • 0 comments

    FPGA Device

    • Stratix II GX EP2SGX30CF780CSN Device
    • 30K Programmable Logic Elements
    • M4K RAM blocks (128×36 bits) - 144
    • M-RAM blocks (4K×144 bits) - 1
    • Transceiver data rate 600 Mbps to 6.375 Gbps

    Configuration and Debug

    • Serial Configuration Device EPCS16N on FPGA
    • JTAG

    Expansion I/O

    Display

    • DVI RX over Sil7181 (no datasheet)

    Switches, Buttons, LED, and 7-Segments

    • 3 LEDs
    • 8 Slide Switches

    Power

    • 12V DC input

    Limitations

    • Quartus II Web Edition - 11.0sp1 -- ATTENTION. There is no complete certainty!
    • Quartus II Subscription Edition - 13.0sp1
    • It is impossible to find documentation on the Sil7181 chip.

    Block Diagram

    IC list:

    U1 GS2974A 4483E3 1052 GENNUM
    U2 IDT Q53VH25 7QG Z41104K
    U3 EL4511CUZ B1047BF4T
    U4 Silicon Image VastLane Sil7181CMHU-0 Q3F619.1-18 1111 AD01KX2
    U5 551MLF 1221868 1103
    U6 664G03LF 1415966 1112
    U7 ZGAH
    U8 M 834U 0496
    U9 (5-PIN)
    U10 (5-PIN)
    U11 EP2SGX30CF780CSN
    U12 EH11A 109N77
    U13 L1BH
    U14 527R-01LF 1814763 1114
    U15 EPCS16N 9911EV5 PHL101
    U16 431 (3-PIN)
    U17 6549CBZ V1052TS
    U501 EH11A 109N77
    U503 GS2978 4371E3 1048 GENNUM
    U504 GS2978 4371E3 1048 GENNUM

    Pinout

     EP2SGX30_sdi_hack.v

    module EP2SGX30_sdi_hack (
    input REFCLK0_B13, //148.5 MHz
    output GXBTX_0,
    output GXBTX_1,
    output SD_HD,
    output [2:0] LED,
    input [7:0] SW,
    output [15:0] DEBUG
);
endmodule

    EP2SGX30_sdi_hack.qsf

    set_location_assignment PIN_J1 -to REFCLK0_B13
set_location_assignment PIN_J2 -to "REFCLK0_B13(n)"

set_location_assignment PIN_E4 -to GXBTX_0
set_location_assignment PIN_E5 -to "GXBTX_0(n)"
set_location_assignment PIN_C4 -to GXBTX_1
set_location_assignment PIN_C5 -to "GXBTX_1(n)"

set_location_assignment PIN_C28 -to DEBUG[0]
set_location_assignment PIN_D28 -to DEBUG[1]
set_location_assignment PIN_D27 -to DEBUG[2]
set_location_assignment PIN_E28 -to DEBUG[3]
set_location_assignment PIN_F28 -to DEBUG[4]
set_location_assignment PIN_F27 -to DEBUG[5]
set_location_assignment PIN_G28 -to DEBUG[6]
set_location_assignment PIN_G27 -to DEBUG[7]
set_location_assignment PIN_H28 -to DEBUG[8]
set_location_assignment PIN_J28 -to DEBUG[9]
set_location_assignment PIN_J27 -to DEBUG[10]
set_location_assignment PIN_K28 -to DEBUG[11]
set_location_assignment PIN_K27 -to DEBUG[12]
set_location_assignment PIN_L28 -to DEBUG[13]
set_location_assignment PIN_M28 -to DEBUG[14]
set_location_assignment PIN_M27 -to DEBUG[15]

set_location_assignment PIN_B10 -to SW[0]
set_location_assignment PIN_A10 -to SW[1]
set_location_assignment PIN_C8 -to SW[2]
set_location_assignment PIN_A9 -to SW[3]
set_location_assignment PIN_B8 -to SW[4]
set_location_assignment PIN_A12 -to SW[5]
set_location_assignment PIN_A7 -to SW[6]
set_location_assignment PIN_A8 -to SW[7]

set_location_assignment PIN_AB9 -to LED[0]
set_location_assignment PIN_AC9 -to LED[1]
set_location_assignment PIN_AD10 -to LED[2]

set_location_assignment PIN_AH7 -to SD_HD

    Pulse and Square wave Generator.

View all 3 project logs

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Discussions

Tom Verbeure wrote 11/18/2019 at 17:28 • point

Here's my write-up on the HWIC-3G-CDMA: https://tomverbeure.github.io/2019/11/11/Cisco-HWIC-3G-CDMA.html

In additional to getting a blinky, I also have the SDRAM half-way up: it's not fully working because Quartus refuses to apply all timing constraints for reasons so far unknown. But I hope to clear the hurdle soon.

The MegaCore DDR controller is time limited unfortunately and only works when your board is tethered over JTAG to the PC. Hopefully somebody can make it work with an open source DDR SDRAM controller (like the LiteX DRAM controller.)

  Are you sure? yes | no

Tom Verbeure wrote 11/11/2019 at 23:12 • point

I spent some quality time reverse engineering the Cisco VWIC3-2MFT board, but ultimately had to give up because the Stratix II on that board requires the Standard (paid) version of Quartus. The free Quartus Web Edition only supports the lowest Stratix II FPGA. 

For those who are interested, my archived results are here:  

https://github.com/tomverbeure/cisco-vwic3-2mft

  Are you sure? yes | no

MorriganR wrote 11/12/2019 at 20:35 • point

Cool work! But this Cisco module is named VWIC3, not VWIC2. VWIC2 contains Xilinx FPGA.

About Quartus Web Edition, I took this information from Intel site, I don't have installed Quartus II Web Edition - 11.0sp1. Can you check if it supports Stratix II GX EP2SGX30CF780CSN Device? 

As far as I know VWIC3-1MFT (module with one E1-port) contains EP2S15. :)

  Are you sure? yes | no

Tom Verbeure wrote 11/12/2019 at 21:57 • point

Ouch, I have a VWIC3 indeed. I have changed the repo name (including the link above) and documentation. I did check with 11.0sp1: it works fine when I select an EP2S15, but not when I select the EP2S30. 

Ultimately, the HWIC-3G-CDMA is a better choice: it has an EP2C35 which is supported until  13.0sp1. I have reproduced your blinky code, and much more. I'll publish that repo soon.

Thanks for the tip about the VWIC3-1MFT. I'll check it out.

  Are you sure? yes | no

Occamlab wrote 11/14/2019 at 08:07 • point

The main disadvantage of HWIC-3G-CDMA is that it has a DDR2 SDRAM memory chip installed, if I remember correctly. This is not the best option for an entry-level board, SRAM is easier to use.

  Are you sure? yes | no

Tom Verbeure wrote 11/14/2019 at 14:11 • point

I hope it won’t be too much of a problem: it has DDR, not DDR2, and the Quartus 11.0sp1 MegaWizard has direct support for the exact Micron DDR that is on my board.

Getting the DDR working is high in the list.

IMO the biggest negative of all these boards is the lack of serial flash, meaning you need some external microcontroller to make a self-hosting solution. I’ve already mapped out connections between the passive serial pins and the HWIC connector.

  Are you sure? yes | no

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