Computer design goals:
RISC-like – inspired by MIPS, but is quite different. This is Load/Store architecture, meaning that ALU operations are only applied on data in registers, and for using data from memory it should be first loaded to these registers, or stored from them back to memory, in separate instruction cycle.
16-bit computer, 16-bit wide registers, 16-bit wide ALU and 16-bit bus.
Memory consists of 16-bit words.
Up to 8M bytes can be addressed, byte-addressable memory.
Component base: 74HCxx SSI and MSI chips (Elementary logic, multiplexers, flip-flops, 8-bit registers, and counters).
Output: Monitor (TV) characters, pseudographics, bitmap.
Mass storage: 1GB CompactFlash card through Parallel ATA interface.
Register file: 8 16-bit registers, 2-address/3-address
First address read-write access, provides A operand for ALU and is overwritten by ALU (when write-enabled), gets written to from bus and enabled to bus.
Second address is read-only, provides B operand for ALU.
First address (A operand) is written with result of ALU operation on 2 registers (B and C operands). C operand has restriction that it cannot be GPR0 or GPR1.
Program counter: presettable synchronous counter – 24 bits
Instruction register: holds running instruction.
Memory address register – 24 bits, can address up to 16M locations
Stack pointer: presettable synchronous up/down counter – 24 bits
Frame pointer: special 24 bit register for temporary storage of SP value.
Functions: ADD, SUB, AND, NOR, XOR, SHIFT, ROTATE
B operand modifications: no, invert (1-complement), twos complement, replace with: 0, 1-255.
Adder: fast adder (with carry look-ahead) for high speed.
Address AU ( 24-bit )
Arithmetic unit, add and subtract for indexed address calculation.