The last time I made update to FSM design, it turned out working ok. But, returning to it now, I find that there is still room for improvement, especially regarding overall sequencing of micro-instruction stages.

The overall sequence is as following: at the falling clock edge a new state is entered, and appropriate signals for selectors, bus drivers and register addresses to be written (write enable lines) to percolate through combinational logic circuits. Then, at the rising clock edge, all the registers (which have their write enable signals HIGH) get new data latched. Regarding data processing, as in example below for ALU instruction: the instruction itself has several bits that are used almost directly to set the ALU to do what instruction says, so the operation begins when there is still Fetch state. This gives time until next rising edge for it to output its result. On the other hand, between starting memory access operation (fetching instruction) and latching the value there is only half a cycle, which makes addressing very constrained by time available. The other half cycle for memory access is idle.

Here is the example timing diagram showing this:

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I think, there is a way to make memory access time a full cycle, with moving setting of the select and enable signals at the rising edge. This will make them seem to be at the same time as latching, but in fact, the latching will be for values from previous micro-op, and there will be delay between rising clock edge and update to select/enable signals because they will be delayed by intervening combinational logic.

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New clock cycle starts right after the rizing edge, when all registers have latched previous values. These values now determine what will go on in this cycle.
The state transitions should be somewhat offset from the main clock rising edge. Previously it was done via making these transitions go on clock falling edge. This works, but for some micro-ops, like fetch, it leaves only half of the cycle to put address to memory bus, and retrieve the stored value. As
memory has latency in range 50-120ns (depending on IC used), this places a constraint on the overall frequency of operation. The other half cycle of fetch is used for decoding the fetched instruction opcode. As this is pretty fast (a couple of gate delays), most of the half-cycle gets unused.

Now, the new scheme strives to reduce the time for opcode decoding to a minimum, and thus use most of the clock cycle for accessing the memory. This also moves the decode part a bit.

The general scheme is:

Previously, the fetch and decode parts were fused together into F1 state. A new
proposal is for fusion of decode and execute phases. At the clock cycle start, Fetch enables the PC value to Address bus, and the Address Adder outputs PC + 2 to Memory Pointers (with PC selected for latch). At the next rising clock edge, the IR is latched with value output from Memory, and PC is latched value output from Address Adder.

On the next clock cycle is Decode fused with Execute. A newly latched value in
 Instruction Register is decoded, and the appropriate state is then activated.
Signal from the newly activated State propagates to set the selectors, enables and latch addresses for particular microinstruction. The rizing clock edge concludes the cycle.

Below is new waveform:

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This, along with tweaks to ISA prompts reevaluation and new update to FSM, on which I am working now.