While trying to accomodate the features provided by funnel shifter, and changing address bus width to 24 bits, I started to look closely into the current Register Transfer scheme, and started to update it. I shuffled around parts of it for more clarity, and for including new features -- I've redrawn the scheme several times by hand, and after having a good variant, I drawn the scheme in Excel (this provides grid, and thus it is easier to make aligned drawings using different cell borders and applying different border styles to them).

Here is the result:

Compressed version:

-----------

Full resolution:

This is quite a detailed scheme, it is advisable to click full-scale by click on the above image.

--------

This updated scheme is also part of the effort to create an emulation of this CPU, about which I'll write in the next log.

Such scheme makes for easier understanding of CPU inner workings, and devising microinstruction sequences for all the different instructions. The image presented is intended to be printed out in several copies for tracing out data propagation and capturing the proper pattern of micro instruction bits. I did the same thing 4 years ago on previous version of RTL scheme, but as I modified it, I need to redo this thing again.