I think I finally got it about how to treat interrupts. 

Well, I thought so 5 years ago (and described the mechanism in the old log). Now, rethinking again, after having read the handbook on pdp-11/40 processor and ARM2 databook, I found out that the dedicated Instruction Vector register is not needed, this address can be supplied directly from EINT instruction.

On the other hand the notion that EINT can be just a jump to subroutine, only with a pre-defined address is missing one component - the saving of current status. Previously I thought that it could be done with additional instruction, but on closer look, this makes some things awkward. So, the EINT should push to stack the SR together with PC. And, as I added the TMP ALU register, that is used as extended carry in some shift operations, it is also should be pushed to stack. In total, 4 words need to be saved, 2 for return address, and SR together with TMP. This now also demands the addition of IRET instruction which properly pops PC, SR and TMP all together so that execution can continue after interrupt as if nothing happened.

Also I think that making the CPU be able to support two modes can be beneficial, and I want to explore this territory. For this to work, at minimum there is a need for additional Stack Pointer, which can be integrated into current design without much pain.