A month ago I decided to create a small rtl emulation of my CPU design, to better grasp high-level view of it, and test some design changes and instruction sequences faster. This simplification was needed, because the model in Digital simulation became too complex and had some bugs with timings that I couldn't fix. Also this complexity would make revision of micro-operation sequencing very difficult.

I thought the task would be simple, and take a week or two, as first idea was to make a list of registers and write some functions that would juggle around values between them. Turned up that it took more time, mostly because I ended up with more thorough simulation, with data structures for registers and busses, and sequential logic for data propagation which itself is often a parallel process. The ALU is just a functional description, but all the plumbing (busses, selectors) between functional blocks are accounted for in this emulation.

Fair bit of time took the re-drawing of RTL scheme, and figuring out the correct data transfers for microinstructions. While doing so I found similarities between several states, and attempted to condense them. This made FSM to contain fewer states, but state transition logic became more complex.

Here is part of the process of figuring out correct paths for data between registers for particular microinstructions:

During this process, I also updated instruction encodings somewhat, and the RTL scheme itself, though marginally.

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I wrote the emulation in C, and for the interface used ncurses library, which proved to be very easy to use, and made me able to concentrate mostly on the workings of emulated CPU, and not spend too much effort figuring out the presentation.

As of the time of writing, current emulation implements most of the instructions, in particular, ALU, memory accesses with all modes, MOVes and jumps (including JSR). Yet to be added are Address Arithmetic, interrupt related instructions and some other miscellaneous ones.

Currently, running emulation looks like this (screenshot):

I think in time I will make it slightly more colourful, but for now it is already very informative. It exposes most of the CPU insides, like register values, a selection of bus values, the control logic state, and control line activation pattern (microinstruction word), and all of the memory (1kB) at a glance. This proved very helpful in troubleshooting this emulation, as well as the little test programs I wrote for it.

It is trivially possible to make the emulation with any memory size up to 16 megabytes, but more than 1kB will be hard to impossible to show at once. And for testing purposes current memory size is quite adequate.

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For now, I am manually assembling the code, as previous assembler version is long been neglected, and as instruction encoding was changed, does not output correct code anyway. When instruction set will be finalized, the assembler will be updated, or rewritten outright.