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Simulation completion

A project log for ECM-16/TTL

16 bit Computer made from ttl logic chips

PavelPavel 11/06/2019 at 06:125 Comments

There was a year long hiatus in my work on this project, but as of recently, I've resumed it.

Looking with fresh eye, I found several things which I hadn't noticed previously, such as commonalities for decode structure in different instructions. This lead to overhaul of decoding circuitry, reducing redundancies while at the same time adding some new instructions ( or rather variations on them ), exploiting found commonalities.

The CPU now is Turing complete. Though there are still possibilities for adding additional instructions, existing set is quite big already.

There are multiple operations for manipulating data with ALU, other ones move data between registers, loading and storing from memory, unconditional and conditional jumps.

The registers are of two types - General purpose (GPR) and Special (SpR). Data in GPR can be manipulated in ALU, while data in SpR can not. Data can be moved between all registers, and also loaded/stored in RAM; although there are some restrictions for particular SpRs.

The ALU can only perform its functions on data from GPRs. Data from memory need to be explicitly loaded or stored as distinct operation.

There is no microcode -- all instructions are decoded by combinatorial logic. 

The computer simulation has very rudimentary I/O as of right now.

It also lacks any interrupt handling.

The last two points will be worked on in the future.

In the Files section there is an archive with simulation files as well as an Excel spreadsheet with all instructions described. It also contains manual "assembler", which makes programming this computer slightly easier.

The simulation files can be opened with Digital logic circuit simulator software.

Discussions

Pavel wrote 11/18/2019 at 19:22 point

I've just found a bug introduced by this new-fangled pre-fetching -- in LD/ST operations, the memory address changed before read operation; now it is fixed by adding 1-gate delay. The files are now updated so these operations are now executed properly.

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roelh wrote 11/18/2019 at 08:23 point

Hi Pavel, can you also supply the files as simple ZIP files ? Makes opening easier.

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Pavel wrote 11/18/2019 at 17:14 point

Zip archive added; contents are the same as in 7z version.

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roelh wrote 11/18/2019 at 17:56 point

Thanks for the Zip file. That's a very ambitious and complex instruction set. Do you have an estimate of the number of IC's ? Perhaps you don't mind how many IC's it takes, but I personally would go for a simpler design. 

Using DIL packages in schematics or simulation makes the circuits difficult to understand, why not use schematic symbols or Logisim/Digital symbols ? That would make it more understandable for your public.

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Pavel wrote 11/18/2019 at 18:46 point

Well, for all circuits I starting with standard symbols, and after proofing the design, I redoing with DIL chips, so it will be easier when I'll start assemble the thing together in real world. The parts made with DILs have their standard logic counterparts, they are all included in archive.

As for ambitiousness, it organically grew from choosing to use 16-bit wide bus. Using 16-bit word makes  instruction encoding easier. For example, the ALU operations are almost directly mapped, and for decoding them, only a handful of gates is needed. This size also made possible to encode a big variety of ALU instructions.

As for memory access instructions, most of complexity grew out of desire to be able to address more than 64k of memory.

As for IC count, I guess it may well be in low hundreds. And it seems most will be multiplexers.

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