There was a year long hiatus in my work on this project, but as of recently, I've resumed it.
Looking with fresh eye, I found several things which I hadn't noticed previously, such as commonalities for decode structure in different instructions. This lead to overhaul of decoding circuitry, reducing redundancies while at the same time adding some new instructions ( or rather variations on them ), exploiting found commonalities.
The CPU now is Turing complete. Though there are still possibilities for adding additional instructions, existing set is quite big already.
There are multiple operations for manipulating data with ALU, other ones move data between registers, loading and storing from memory, unconditional and conditional jumps.
The registers are of two types - General purpose (GPR) and Special (SpR). Data in GPR can be manipulated in ALU, while data in SpR can not. Data can be moved between all registers, and also loaded/stored in RAM; although there are some restrictions for particular SpRs.
The ALU can only perform its functions on data from GPRs. Data from memory need to be explicitly loaded or stored as distinct operation.
There is no microcode -- all instructions are decoded by combinatorial logic.
The computer simulation has very rudimentary I/O as of right now.
It also lacks any interrupt handling.
The last two points will be worked on in the future.
In the Files section there is an archive with simulation files as well as an Excel spreadsheet with all instructions described. It also contains manual "assembler", which makes programming this computer slightly easier.
The simulation files can be opened with Digital logic circuit simulator software.