JOYMEGA MODE

During the execution of the JOYLIB.GTJOYMEG6 from HIDLIB, the Z80 calls a function to read the Joystick right after it flips the state of the Pulse pin ..

...
    call    BASELIB.FLIPPORTOUT    ;
    call    BASELIB.RDJOYPORT;
..

Tracing the assembly instructions the time it takes from the pin change (OUT instruction)  to the reading (IN) is 100 cycles  (see below) or ~28us.

In terms of AVR cycles it means 100 * (8MHz/3.58MHz) or 223 cycles to spend with latency. After discounting 11 cycles for the latency of a pin change interrupt theres is still more than enough processing time for not to worry with the compiler overhead.

call    BASELIB.FLIPPORTOUT 
    BASELIB.FLIPPORTOUT:    
    ld    a,e
    xor    d        ; flip Output
    ld    e,a
    ld    a,15
    jp    WRTPSG    
    
    WRTPSG:
    DI
    OUT    (PSG.LW),A    ;LATCH ADDRESS
    PUSH    AF
    LD    A,E
    OUT    (PSG.DW),A    ;OUTPUT DATA  ; 12
    EI                                 ; 5
    POP    AF                          ; 11
    RET                                ; 11
 
  
call    BASELIB.RDJOYPORT              ; 18
    BASELIB.RDJOYPORT: 
    ld    a,14                         ; 8 
    di                                 ; 5
    call    RDPSG                      ; 18
    RDPSG: 
    OUT    (PSG.LW),A                  ; 12 
    IN    A,(PSG.DR)   
    RET    
    ei
    ret
; 12+5+11+11+18+8+5+18+12 = 100
 

BASIC MODE

The timing on Basic mode is a bit shorter, 60 cycles from the instruction that rise the level of the Pulse pin until the first reading on the joystick port.

It is still enough time to deal with the code produced by the compiler as it represents ~17us  or 134 AVR cycles (at 8MHz).

GTPDL:
    INC    A        ;Force parameter 2 based
    AND    A
    RRA
    PUSH    AF        ;Save port # (carry reset if port 1)
    LD    B,A
    XOR    A
    SCF
PDL1:
    RLA            ;Form mask pattern
    DJNZ    PDL1
    LD    B,A        ;Set mask pattern
    POP    AF
    LD    C,10H        ;Assume port 1
    LD    DE,03AFH
    JR    NC,PDLP1    ;Good assumption
    LD    C,' '
    LD    DE,4C9FH
PDLP1:
    LD    A,PSG.PB
    DI
    CALL    RDPSG        ;Get current port B content
    AND    E
    OR    D
    OR    C                                             
    OUT    (PSG.DW),A    ;Set trigger high       ; 12
    XOR    C                                     ; 8
    OUT    (PSG.DW),A    ;Set trigger low again  ; 12
    LD    A,0EH                                  ; 8
    OUT    (PSG.LW),A                            ; 12
    LD    C,0        ;Initialize counter         ; 8
PDL2:                                            ; total: 12+8+12+8+12+8 = 60
    IN    A,(PSG.DR)                             ; 16.76us / 134 AVR cycles @ 8.0 MHz 
    AND    B        ;End of pulse?
    JR    Z,PDL3        ;Yes
    INC    C        ;Bump counter
    JP    NZ,PDL2        ;No overflow yet
    DEC    C        ;Make it 255
PDL3:
    EI
    LD    A,C        ;Return counted value
    RET