The general concept is based in my other early RISC processors and composed by a simplified two stage pipeline where a instruction is fetch from a instruction memory in the first clock and then decoded/executed in the second clock. The pipeline is overlapped without interlocks, in a way the darkriscv can reach the performance of one clock per instruction most of time (the exception is after a branch, where the pipeline is flushed and one clock is lost). As addition, the code is very compact, with around two hundred lines of obfuscated but beautiful Verilog code.

Although the code is small and crude when compared with other RISC-V implementations, the darkriscv has lots of impressive features:

• implements most of the RISC-V RV32I instruction set (optional RV32E)
• 2 stage pipeline (optional 3-stage pipeline)
• works up to 100MHz and sustain 1 clock per instruction most of time
• flexible Harvard architecture (easy to integrate a cache controller)
• works fine with gcc 9.0.0 for RISC-V (no patches required!)
• uses around 1k LUTs (Spartan-6, core only)
• permissive BSD license

Feel free to make suggestions and good hacking! o/