I added support for Yosys finite state machine transformations. If Yosys recognizes your code as a finite state machine, you can now opt to have the FSM represented as a single circuit element. You can then see the FSM as a graph, with the current state highlighted.
Another important change for this release is more (time- and space-) efficient memory representation. This allows faster synthesis and simulation of circuits containing memory images.
Two big features went online recently: memory editor and triggers.
Memory editor allows to inspect the contents of ROM/RAM cells and to modify it. The feature is especially important for simulating CPUs and similar circuits. If a register bank is implemented via a multi-ported RAM, its contents can be inspected thanks to this feature.
Triggers allow to stop simulation on a certain event: an edge for a one-bit signal, or a value appearing on a multi-bit signal. This feature is meant to be a help for debugging circuits. Single-stepping synchronous circuits got easier: you can now trigger on a clock signal, and then fast-forward to the next clock edge.
For a long time, the project had a slight performance problem. Because of how the JointJS library - which is used to display gate schematics - is designed, a lot of unnecessary DOM calls were happening, which were slowing things down. Fortunately, recently a new version of JointJS was released, which addressed this very problem. As a result, displaying larger schematics is now much faster.
I've extended DigitalJS so that one can display waveforms for selected wires in real time. Just hover the mouse over a wire, click the blue loupe icon, and that's it! The waveform display can be mouse dragged, and the scale can be changed by using the mouse wheel. I tried to make the display as readable as possible. Please let me know about any issues you find!