Memory editor and triggers

A project log for DigitalJS

In browser visual simulation of Verilog code

Marek MaterzokMarek Materzok 08/13/2019 at 21:040 Comments

Two big features went online recently: memory editor and triggers.

Memory editor allows to inspect the contents of ROM/RAM cells and to modify it. The feature is especially important for simulating CPUs and similar circuits. If a register bank is implemented via a multi-ported RAM, its contents can be inspected thanks to this feature.

Triggers allow to stop simulation on a certain event: an edge for a one-bit signal, or a value appearing on a multi-bit signal. This feature is meant to be a help for debugging circuits. Single-stepping synchronous circuits got easier: you can now trigger on a clock signal, and then fast-forward to the next clock edge.