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Finite state machines

A project log for DigitalJS

In browser visual simulation of Verilog code

Marek MaterzokMarek Materzok 09/19/2019 at 17:180 Comments

I added support for Yosys finite state machine transformations. If Yosys recognizes your code as a finite state machine, you can now opt to have the FSM represented as a single circuit element. You can then see the FSM as a graph, with the current state highlighted.

Another important change for this release is more (time- and space-) efficient memory representation. This allows faster synthesis and simulation of circuits containing memory images.

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