STM8S Medium Density devices can have "Performance" too!

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ThomasThomas 01/07/2020 at 21:032 Comments

For some reason only product line managers and heads of marketing departments will understand a part of STM8S "high density" chips have been placed in the "Performance Line".

The rationale?

Maybe the 24MHz specs (instead of just 16MHz). OK, the datasheet says "0 wait states @ 16MHz). The datasheet promises 20MIPS @ 24MHz. Big deal - for a chip that's considerably more expensive (at low quantities) than an STM32F103CBT6.

On the other hand, if one wants to use an STM8S005C6T6 (about $0.40 @ 10pcs incl. shipping) with an 10MHz internal clock for peripherals, one can't simply use a 20MHz crystal and add that "1 wait state": the data sheet doesn't mention such a feature (the chip is "Value Line", not "Performance Line" after all!

On the other hand, I've learned to take ST's STM8S datasheets with a grain of salt, or Доверяй, но проверяй!

I quickly typed the following mini-benchmark into an STM8S005C6T6:


: test TIM 100 FOR 
    32000 FOR 
      I DUP * DROP 

test 6865 ok

The code does 3232101 (101 * 32001) multiplications  and measures the execution time in background ticks (at a 5ms interval). The time is thus 34.325 s (10.6 µs per iteration).

Now I ignore the description "Option byte 7: Reserved" in the datasheet and instead use the description for setting "1 wait state" from the STM8S207 datasheet:

(base) thomas@w500:~/source/stm8s/stm8ef$ echo "00 00 ff 00 ff 00 ff 00 ff 00 ff 00 ff 01 fe 00 ff" | xxd -r -p > set_opt7_to_1.bin 
(base) thomas@w500:~/source/stm8s/stm8ef$ stm8flash -c stlinkv2 -p stm8s103f3 -s opt -w set_opt7_to_1.bin
Determine OPT area
Writing binary file 17 bytes at 0x4800... OK
Bytes written: 17

The STM8S005 restarts and I re-run my simple benchmark:

test 8247 ok

8247 * 5ms = 41.235s, that's a lot slower (12.74 µs per iteration) a clear sign that the wait state works!

A quick check:

6866 / 8247 * 24 MIPS  = 19.98 MIPS.

So, should I use a 24MHz crystal and 1 wait state i'd, have a "performant" (20MIPS) "Medium Density" (STM8Sx05) "Value Line" chip.


Datasheets of automotive "Medium Density" devices, like STM8AF6266, confirm the wait state bit in the configuration location OPT7. The STM8S family (including the automotive STM8AF) appears to have more line managers than chip designs, but if one is interested in STM8S chip properties, STM8AF datasheets are  a good place for testing assumptions.

There, and in old versions of the RM0016 STM8AF/STM8S reference manual, one can also uncover what OPT6 and the TMU is all about. Interesting stuff for protection of IP in production systems, but I'm not sure if it will ever be relevant for hobby projects. One hint anyways: if one doesn't care about TMU one can safely store an arbitrary 8bit value in OPT6 ($480B). 

One more thing I tested in Low Density devices: while a EEPROM cell exists for configuration byte OPT7 in both Low Density chip variants (commercial STM8S103 and STM8S903, or automotive STM8AF6223 and STM8AF6223A), bit0 doesn't cause a wait state.


Ken Yap wrote 01/07/2020 at 21:48 point


But I'm confused by the arithmetic. If I understand correctly you took a value line chip, altered the option byte but you are still running it at 16MHz, thus slower than the presumably identical performance line counterpart running at the top speed?

How is the ratio 5/6 related to the ratio of the clock speeds? Wait state comes into it?

  Are you sure? yes | no

Thomas wrote 01/08/2020 at 15:58 point

In my experiment I took  a "Value Line - Medium Density" chip and used 1 WS at 16 MHz HSI.

My observations are in line with the 20% performance penalty as the result of adding a wait state that ST mentions in the "Performance Line - High Density" datasheet (e.g. STM8S207). Low Density chips (e.g. STM8S003) don't show the performance drop which means that wait states can't be configured, at least not in the same way as for the other families.

You're right, the math above isn't quite correct. A STM8S005 operating with a 20 MHz clock and 1 WS should have about the same performance as one with 16.7 MHz clock and 0 WS.

Hence,  "19.2 MHz @ 1 WS"  should have same performance as "16 MHz @ 0 WS".

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