To have a quick start, a very simple instruction set was chosen. It is based upon the zero-page addressing mode, and most operations work on 16-bit values. This makes it a 16 bit processor with an 8 bit bus. There is a single 16-bit accumulator, surprisingly called "A", and a 16-bit PC. A single instruction can load or save the 16 bits in A from or to the zero page. Also, the zero page values can be used as a pointer (as in the 6502) . This makes indirect load or store possible. There is an increment-by-two that works with a table in external ROM. All instructions are two bytes long. The opcodes are simply the 8-bit start addresses in the microcode, 16 bytes apart, giving a maximum of 16 opcodes. It is not an efficient opcode since only 4 of the 8 bits in the opcode are used.
Note that these instructions can be (almost) freely chosen, but that they must be supported/interpreted by the microcode program. To support this simple instruction set, the microprogram is less than 256 bytes. 4096 bytes are available, so a much more complex instruction set can be supported.
0 - 3FFF RAM
4000 - 7FFF I/O
8000 - BFFF ROM
'A' is a 16 bit accumulator in RAM at 0x0004(lsb) and 0x0005(msb) PC is a 16 bit location in RAM at 0x0002(lsb) and 0x0003(msb). (Execution starts at 0x8010) Temp is a 16 bit temp storage in RAM at 0x0006(lsb) and 0x0007(msb) reset vector: Address 0x8000 in ROM contains fixed value 0x10, address 0x8001 contains 0x80 address 0x8002 contains 0x00 The following opcodes are defined. All opcodes are followed by a single operand byte. 0x20 LDB AL,#I8 ; 8 bit immediate load AL, AH will be set to zero. 0x30 LDB AH,#I8 ; 8 bit immediate load AH 0x40 LDW A,Z ; 16 bit load from a zero page location 0x50 STW Z,A ; 16 bit store to a zpage location 0x60 LDW A,(Z) ; 16 bit indirect load (address pointer in zero page) 0x70 STW (Z),A ; 16 bit indirect store (pointer in zero page) 0xe0 LDB A,(Z) ; 8 bit indirect load (address pointer in zero page) 0xd0 STB (Z),A ; 8 bit indirect store (pointer in zero page) 0x80 BR label ; replace lower 8 bits of PC 0x90 BRM label ; replace lower 8 bits of PC if bit 7 of ACC is 1 0xa0 BRP label ; replace lower 8 bits of PC if bit 7 of ACC is 0 0xb0 PAGE label ; jp to another page, label is 16 bit (lower 8 bits ; must be zero, so it's a 2 byte instruction) 0xc0 INCD A ; 8-bit increment-double (increment-by-two) accumulator (needs table in ; ROM at 0x8100) ; The second instruction byte has msb of table address ; The same table is used to increment the PC. 0xc0 DECD A ; 8-bit decrement-by-two accumulator (needs table in ROM ; at 0x8200) ; The second instruction byte has msb of table address