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A long overdue update - ASIC replication and VHDL

A project log for The Last Psion

Resurrecting Psion's SIBO/EPOC16 Platform For The 21st Century

alex-brownAlex Brown 10/30/2019 at 14:422 Comments

It’s been far too long since my last update on this project. It’s the usual excuse (“I’m sorry, but life just got in the way, blah blah blah.”) and to those of you who are taking an interest in my little WiFi Pack project, not to mention the rest of the efforts of the Last Psion project, I can only apologise. For now, here’s a brief update on what I’ve been up to.

My focus has shifted slightly, away from SIBODUMP and other C projects, over to the little chip pictured above. It’s Psion’s ASIC4, described by Psion themselves as “a serial protocol slave IC for addressing memory and general memory-mapped peripherals.” I’ve long thought that this wee beasty has been the key to getting the WiFi Pack working.

So, why pick ASIC4 instead of its older sister, ASIC5? Well, while ASIC5 is a very versatile chip (on-board UART, for example), it doesn’t offer as many options for peripherals. While ASIC5 can address 8MB of storage. ASIC4 can address up to 256MB split 50-50 between storage and peripherals.

ASIC4 is, of course, no longer being manufactured. Right now the only plentiful source of ASIC4s is the selection of SSDs that appear regularly on eBay. While this would certainly provide me with the silicon that I crave, it would also take SSDs off the market. It would also leave me with a large number of dead SSDs cluttering up my desk.

PCB of a ROM SSD (Autoroute) using ASIC4.

As with all similar retro projects, this has left me with a dilemma. Do I accept that I will be responsible for the massacre of countless retro storage modules? I think sacrificing a couple of copies of Autoroute for The Greater Good is acceptable, but it’s certainly not sustainable. What I really need is a way to make more ASIC4s.

Cue the wonderful world of FPGAs!

Also, cue headaches and defeatism while I try (and repeatedly fail) to learn VHDL.

And this is where I am right now, learning VHDL and digital design in general while trying to understand exactly how ASIC4 works. And I’m not going to lie, I’m not enjoying it as much as I wish I was. I like being creative, and right now it feels like there’s very little creativity in studying.

The creativity will come, of course. Once I have a working ASIC4 replica I will be able to modify it to my heart’s content. For example, how about adding an I2C interface? Or SPI? Or even a Z80 for some weird retro-on-retro gaming?

And yes, I know I could try to emulate ASIC4 in code rather than simulate (replicate?) it in hardware. The trouble is, I want to create something that fits into the SSD slot of a SIBO machine, something that’s ultra portable so that the user (i.e. me) doesn’t have to worry about forgetting to bring yet another device with him. A Raspberry Pi is just too big for this, and an ESP8266 is just too slow. ASIC2 and ASIC9 (the main ICs in the early and later SIBO machines) require immediate response from anything connected to them using SIBO-SP. If an ESP unit is busy doing other things, corruption will occur.

So, to you lovely hardware hacking people, I have a request. I would like to hear of projects where people have tried similar things, preferably by people who were, when they started, just as much of a newb when it comes to FPGAs as I am now.

Answers on a postcard, please. Or just in the comments below.

Discussions

ferry.haentsch wrote 04/20/2023 at 16:24 point

Hi again. Just found, what i was looking for in the "THE PSION SIBO HARDWARE D EVELOPMENT KIT".

http://www.scss.com.au/family/andrew/pdas/psion/hdk.pdf  page 26.

nice. :-)

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ferry.haentsch wrote 04/20/2023 at 16:11 point

Hi Alex,

 I just found your pinout image of the ASIC4. It seems you know a lot of these different PSION-ASICS, but do you also know how to configure them for the different flash-chips and memory-sizes? What i see is that there are strapping resistors on the 8 Data-lines (D0-D7) that can either be connected to GND or VCC. In the Flash-modules i own (128kB, 512kB, ASIC4 type) only the lower 5 bit are configurable, the upper 3 bit also have strapping resistors, but with fixed potential.

With your pinout-picture i know how to connect bigger flash-chips, thats very helpful, but what about the configuration?

Since i would like to have at least a few MB within one module it would be interesting to know, how the 8 (or more?) bit have to be configured/strapped.

Thank you very much.

ferrytale

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