When you are running simulations in Verilog, you might notice that many of the files will have a directive like this:

`timescale 1s/1ms

This tells the Verilog simulator how to mark time. What the line above means is that you want to express delays in seconds and the simulator should keep track of time down to 1 millisecond. You have to use a "decade" number for the first number. So 1, 10, or 100. You can't use 20 or 1000 or 0.5. But you can use different units. For example, instead of saying .1 seconds (which is illegal) I could say 100ms.

Suppose you have this code in y our simulation:
 

#10 reset=1'b1;

If the timescale above was in force, the simulator will multiply 10 by 1 second so that delay is a 10 second delay. It will also track the time down to 1 millisecond, although that's not important in that case. However, I can also specify delays that are fractional:

`timescale 1ms/10us
#0.333 reset=1'b1;

In this case, the computed delay is 333uS but since the precision is only 10uS, the simulator will treat it as 330uS.

The truth of it is, you don't have to have a timescale if you don't mind doing your own math. But it does make it easier to have a meaningful timescale, set your clocks to the right frequency, and then have proper time readouts in your waveform viewer.

You can see an example of this in the final project for this bootcamp.