Alexander NekhaevSystemVerilog source code of vanilla TD4 is now available on GitHub in main repo.
SystemVerilog sources added
A project log for 4-bit CPU (TD4 once again)
I build TD4 CPU and expand it (add RAM, switchable memory banks and rugged I/O)
A project log for 4-bit CPU (TD4 once again)
I build TD4 CPU and expand it (add RAM, switchable memory banks and rugged I/O)
SystemVerilog source code of vanilla TD4 is now available on GitHub in main repo.
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