With a continuity tester, I worked out the decoder logic for the memory space:

ROM: /CS = /MR + /A15

RAM: /CS1 = /MR + A15, CS2 = /CS1 (jumper option 1) or A13 (jumper option 2)

For the ROM, this means that the address space is from 0x0000 to 0x7fff, working in inverted logic since the CS line is negated. The A14 line however needs to be rewired to the CPU for the full 32kB space, currently it's pulled high, which doesn't matter to the existing 2764 EPROM.

For the RAM, this means that the address space is potentially 32kB. For this the bridge has to be moved to the A13 line since the CS2 pin becomes the A13 pin on larger RAM chips. The A14 pin is already wired to the CPU but is a NC pin on the current 8kB RAM.

This means I can write fairly large programs using lots of data (by Z80 standards).