Opensource VHDL synthesis support

A project log for netpp node

Networked remote control on FPGA SoC

MartinMartin 02/22/2020 at 09:250 Comments

Slowly getting there: the yosys OpenSource toolchain has proven stable for the Verilog world, now an early development release of MaSoCist CPU builds for VHDL output is spinning on two Lattice ECP5 development kits:

There are two CPU architecture configurations possible:

Find the quick start instructions (Docker based) here.

Don't get too hyped on the RISC-V yet: Due to a lazy workaround implementation of the dual port RAM, the compiler may spit out code that is not correctly working due to a missing read-during-write scenario. A workaround could be to cover for this 'hazard' in the pyrv32 core.

Next step is to look at the rather crucial TDP (true dual port) RAM inference. Once this is working, I'm confident that all regression tests will pass.

A very pleasant little detail: JTAG access is working correctly and stable, so that we can debug the hardware in detail and do the same regression tests as done in the simulation.