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Steve's board

A project log for STEbus Z80 and FDC

STEbus Z80 and FDC, with 64K DRAM, and SCC. Renovation project, not my own design.

keithKeith 11/13/2022 at 13:420 Comments

Steve reported some problems with his board. The reset generator (IC9, SN74LS123, a dual monostable) was holding the reset lines to the FDD controller and Z80 low. It should reset the FDD controller first, then the Z80. Not having a spare to hand he replaced the IC with a header containing 2 RC circuits, and the Z80 now starts reliably, so the EPROM content is probably good.

I suspect the 4µ7 electrolytic capacitor C10, controlling the reset pulse, will have dried out and needs replacing.

The FDD controller does not appear to be working correctly. Whe put it into 'test' mode as described in appendix E of the manual, the VCO clock was not running. 

If the FDD controller is dead it may be difficult to replace - Cricklewood Electronics stock the WD2793 for £78 and the WD2797 for £15 but not the WD1791. The WD2797 is not compatible because pin 25 is the Side Select Output instead of Enable Mini Floppy input. The SCPUA board has this pin wired to the 5/8 inch drive size select, so there would be two outputs driving the same wire.

The WD2791 FDC chip is still obtainable (£30 from ebay).

The WD2793 is similar but with a true data bus ( £28 from ebay) so the latter could be used with trivial mods to the firmware. I have added conditional assembly to the firmware so it can assemble for either the 2791 or 2793. As a bonus, the disk i/o will run slightly faster, because the disk data does not have to be inverted by software.

The 2793 is used in the Atari 800 series machines, and is available from Best Electronics for $16

FDC chip supply was a headache even in the 1980s. The WDx79x chips came in four variations, and if one of them became unobtainable then you were stuck. For this reason, Arcom's FDC board was designed to use any variant, by having the chip data passed through inverting or non-inverting buffers, and having the functions that differed controlled by TTL chips instead.

2022-11-18

Steve's SCPUA arrived. Known-dead LS123 removed, destroyed, and replaced with my (presumably working) LS123 from my board. 

I flipped it over to look at the underside, instantly spotted two unsoldered pins! Pins 8 and 9 of IC11, a 74LS93, drive the master clocks CLK2 (2 MHz to the FDC) and CLK4 (4 MHz for the CPU and DRAM controller). Joints now soldered.

It has no serial number. The test department only assign serial numbers to boards that pass testing. Maybe it missed the test procedure?

2022-11-20

5V applied to Steve's board. A quick probe of important pins:

IC10 (CPU)
6 CLK 4 MHz
26 /RESET 5V DC
19 /MREQ 1.2 MHz
21 /RD 0.9319 MHz
22 /WR 0.1794 MHz
27 /M1 0.4 MHz

IC12 (TMS4500)
1 CLK 8MHz

IC18 (FDC)
24 CLK 2 MHz
19 /MR 5.04 V DC
3 /CS 4.723V 0.16 MHz

IC15 (SCC)
20 CLK 4 MHz

IC9 (74LS123 reset circuit)
2 B 2.562 V DC
4 /Q1 5.046 V DC

IC8 (ROM) 
20 /CS 0.8 MHz
22 /OE 0.931 MHz

Looks good so far. Healthy clocks, out of reset, accessing the ROM and FDC chip. Next step is to see if the sign-on message appears. Steve said it already got that far, but failed to recognise a CP/M disk from the 1980s. Following the instructions in appendix E of the SCPUA manual (connect pin 22 of the disk controller to pin 20 (ground)), he found that the VCO (as measured on pin 16) was not working. He has some doubts about the instructions in appendix E, as the value measured for step (3) was quite a bit different from the target value of 500ns. I shall make a note of the observed settings before making adjustments, just in case the instructions are wrong.

I need a break to find my collection of FTDI USB to Serial interfacing cables and dongles.

I read the three PAL chips and disassembled the logic, and put the pin names in. This clarified a lot of the workings. They differ a lot from my two logic chips, which don't seem to make great sense, so I suspect they were just prototype or junk. 

I shall copy Steve's PAL logic to some new GAL 16V8  chips for my board, and create a boot ROM modified for my FDC chip. Tandem debugging may help - what they do the same is probably right, and if they differ then one of them must be wrong.

2022-11-23

I soldered on a ground wire (for the scope) and a switch for joining the FDC pin 22 to ground. Tweaking the trimmer devices adjusted the signals on pins 29, 31 and 16 as expected. I forgot to measure what they were to start with, but left them in state expected. The master clock is 2 MHz. It is not possible to adjust the VCO to 250 kHz ±5 kHz by eye, I shall fine-tune it by measuring the frequency with a multimeter.

That done, it will be ready to try with a floppy disk drive.

2023-01-13

Timing adjusted, looks correct. Measured on accurate meters.
Made an Arcom RS232 10-pin header to IBM PC 9-way D-type adapter.

2023-01-15

Unable to find 34-way FDD cables! I must have thrown them all out as very obsolete technology. Being impatient, I hacked down a 40-way cable.

Connected board and my own FDD with the sawn-off cable. Placed board in case and switched on. Inserted disk from Steve, and got this:

Press RETURN

Arcom ATLAS
Serial console running at 9600 baud

Insert system disk in drive A: and press RETURN

Error reading system disk:
Track-000, Side-0, Sector-001, Record not found, Retry (Y/N)

This is good in that it got as far as reading the floppy drive. The drive is pretty old, and the eject button is very stiff. 

I tried a different drive, which did not have a stiff eject button. I got this:

Press RETURN

Arcom ATLAS
Serial console running at 9600 baud

Insert system disk in drive A: and press RETURN

Unknown disk format
Insert system disk in drive A: and press RETURN

Not so good. 

At this point I wonder if the board expects something different, such as 8-inch drives instead of 5.25 and 3.5 inch. There are no link jumpers for this.

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