SO, just to extend the brief introduction from the project's home page, this project can be described as an introductory experience for both me and @Neale Estrella. In his case, he's new to the world of RTL design for FPGAs and wants to learn Verilog for behavioral synthesis. For me, my entire FPGA-related experience is with Xilinx FPGAs and for the first time, I want to do a project with an Altera FPGA!
In later projects, I hope to check out Altera's OpenCL support and their Nios II softcore processor! But, similar to how I initially started out, we plan to implement this entire project in Verilog. Once we have the design running over the DE0 Nano, I hope to add circuitry to allow the FPGA toggle an actual lap!
( The lap I want to toggle!!!... Just really wanted to throw in a picture somewhere. )
At this point, we already have a few aspects of the project figured out. As briefly mentioned, we both bought the Terasic DE0 Nano development board. The Nano contains the Altera FPGA, however the board was mainly selected for it's decent cost, peripheral components, and it appears to be fairly popular among other hobbyists who work with FPGAs. As for the development environment, I've started to learn Quartus Prime 16 Lite, but I believe Neale needed to get Quartus II Web instead since he uses a 32-bit system. Pretty sure both are nearly identical! And, of course, we are in the process of learning ModelSim Altera for simulation!
( Looks pretty sweet!!!... Can't wait to actually turn it on! )
As of now, the entire RTL design is, in a way, "finished". In the repository, you can see all the modules. However, only the GetSignal module was fully tested, simulation and deployment. As for the others, my hope is to have a few of them replaced with Neale's implementations.
Finally, in the next several logs, I will explain the theory of operation!