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Version 2.2

A project log for VHDL library for gate-level verification

Hard macros and tiles of Actel/Microsemi's ProASIC3 so I can design and verify optimised code without the proprietary libraries

Yann Guidon / YGDESYann Guidon / YGDES 11/19/2019 at 06:110 Comments

I try to clean up my code and integrate the INC8 unit for a much-needed update and the results are looking good :-)

PA3_genlib.vhdl:151:5:@0ms:(report note): 13x A3P gates found.
PA3_genlib.vhdl:153:7:@0ms:(report note):  gate number: 0  bit number: -1
PA3_genlib.vhdl:155:7:@0ms:(report note):  -- no gate function is altered --
PA3_genlib.vhdl:156:7:@0ms:(report note): List of the registered gates:
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#1 : :inc8_tb(plip):tb@inc8(tiles):e_r0b@inv(trace):lut2
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#2 : :inc8_tb(plip):tb@inc8(tiles):e_r1b@xor2(trace):lut4
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#3 : :inc8_tb(plip):tb@inc8(tiles):e_r2b@ax1c(trace):lut8
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#4 : :inc8_tb(plip):tb@inc8(tiles):e_r3a@and3(trace):lut8
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#5 : :inc8_tb(plip):tb@inc8(tiles):e_r3b@xor2(trace):lut4
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#6 : :inc8_tb(plip):tb@inc8(tiles):e_r4a@and2(trace):lut4
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#7 : :inc8_tb(plip):tb@inc8(tiles):e_r4b@ax1c(trace):lut8
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#8 : :inc8_tb(plip):tb@inc8(tiles):e_r5a@and3(trace):lut8
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#9 : :inc8_tb(plip):tb@inc8(tiles):e_r5b@ax1c(trace):lut8
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#10 : :inc8_tb(plip):tb@inc8(tiles):e_r6a@and3(trace):lut8
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#11 : :inc8_tb(plip):tb@inc8(tiles):e_r6b@ax1c(trace):lut8
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#12 : :inc8_tb(plip):tb@inc8(tiles):e_r7a@and3(trace):lut8
PA3_genlib.vhdl:171:7:@0ms:(report note):  gate#13 : :inc8_tb(plip):tb@inc8(tiles):e_r7b@ax1c(trace):lut8
PA3_genlib.vhdl:228:5:@5120ns:(report note): End of simulation ! 256 cycles.
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(1) = 128 128  |  0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(2) = 64 64 64 64  |  0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(3) = 32 32 32 32 32 32 32 32  |  0 0 0 0 0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(4) = 32 32 32 32 32 32 32 32  |  0 0 0 0 0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(5) = 112 16 112 16  |  0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(6) = 64 64 64 64  |  0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(7) = 56 56 56 56 8 8 8 8  |  0 0 0 0 0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(8) = 32 32 32 32 32 32 32 32  |  0 0 0 0 0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(9) = 84 84 28 28 12 12 4 4  |  0 0 0 0 0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(10) = 48 48 48 48 16 16 16 16  |  0 0 0 0 0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(11) = 98 98 14 14 14 14 2 2  |  0 0 0 0 0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(12) = 105 105 7 7 15 15 1 1  |  0 0 0 0 0 0 0 0  (0)
PA3_genlib.vhdl:242:7:@5120ns:(report note):  h(13) = 105 105 7 7 15 15 1 1  |  0 0 0 0 0 0 0 0  (0)

Basically : if all the mapped gates use the trace architecture, the sub-design under test can be treated as a "black box" and the whole logic network can be re-extracted at will, modified/altered, etc.

v2.2 is now uploaded in the files section as A3Ptiles_v2.2_20191119.tgz

Also notice the histogram result : it gives a very interesting insight into the switching activity of certain nodes and could help with predicting (relative) power consumption in CMOS for example (or noise with relays hehehe)


Once it's done, the rest is just some easy scripting !

The test.sh for the INC8 unit lists all the LUTs and then scans them exhaustively, inserting one fault successively. The 13 LUTs have 86 cases to test and it's completed in a few seconds, without even trying to use multiple parallel instances.

I have therefore proved that my INC8 is not only working, but also leaves no logic hole and will be easy to test with tailored vectors.

Next in line will be the ALU...

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