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A project log for VHDL library for gate-level verification

Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

Yann Guidon / YGDESYann Guidon / YGDES 07/18/2020 at 05:010 Comments

I just added a test of a few DFF ( DFN1E1C0 , DFN1C0 ) in the form of a Gray code counter. This uncovered a biiig bug in my code and libraries, that are now easily solved. Burn all previous versions !

I also rearranged the order of the sanity tests / examples so the shortest come first.

This new release is already 198668 bytes when compressed...

I am now considering how I could integrate the FF in the verification system, they use a LUT2 so far so they are excluded from the algorithm...

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