Let's generate (most) files

A project log for VHDL library of ProASIC3 gates

Hard macros and "tiles" of Actel/Microsemi's ProASIC3 so I can design compatible and optimised code without the proprietary libraries

Yann Guidon / YGDESYann Guidon / YGDES 06/17/2019 at 09:200 Comments

If you remember the log What if we generated the files for each gate ?  you know I discarded the idea of generating the gates with a script.

Well, after a few days of sitting on this setback, I decided that there were enough "low hanging fruits", and the advantages are good enough, to justify writing some code to generate those gates. The trick is to keep the system simple and small enough that it doesn't create more problems than it solves.

The first change is to create 4 types of combinatorial gates, depending on the number of inputs. The sequential gates (latches, flip-flops) will be ignored for now.

4 types means there are dealing with 4 sizes of lookup tables : 1, 2, 4 and 8 entries. Ideally we would use only one size (8 entries) and an extra size parameter (stored somewhere) gives the range, or something... but since VHDL arrays already has 'range-related attributes, we can infer the actual type. The perturbation logic would be something like :

index = Random() mod Table'Length;
table(index) <= table(index) xor '1';

The lookup table array is std_logic_vector because it helps with something else : coverage. If one element of the table is set to 'X' then the value will (ideally) propagate to the output, showing that this entry is sensitive to a given test vector. The universal gate must be modified:

if (a='X') or (b='X') or (c='X') then
    return 'X';
end if;

We can go even further because each input gets compared sequentially to create the index :

variable i : integer := 0;
if a = '1' then
    index := 1;
    if a /= '0' then
        return a;
    end if;
end if;

Then the same code is copy-pasted-modified for b and c, depending on the number of inputs (and names) of the gates.

Sounds like a plan... 

Now that we can deal with a flexible size of lookup table, we can define the corresponding type :

  subtype LookupType1  is std_logic_vector( 0 downto 0);
  subtype LookupType2  is std_logic_vector( 1 downto 0);
  subtype LookupType4  is std_logic_vector( 3 downto 0);
  subtype LookupType8  is std_logic_vector( 7 downto 0);

 Then we can sort the gates according to their inputs :