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What if we generated the files for each gate ?

A project log for VHDL library for gate-level verification

Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

yann-guidon-ygdesYann Guidon / YGDES 06/12/2019 at 00:350 Comments

There are about 100 files of the gate_* form. They are quite hard to manage, though the collection has grown organically and slowly... but if we want to modify them globally, it becomes painful and tedious. Errors could creep into the code and be hard to spot...

Most gates follow a simple pattern : 3 inputs, one output, one boolean function to apply. It seems very easy to script.

Then, there are some gates with a different naming scheme, such as the MUXx gates. OK, so let's have, for each gate, an array of strings with the names of the input signals.

Then, there are gates with only 2, 1 (INV) and even 0 inputs (GND...) so a different/smaller lookup function is required.

And then, there are the sequential gates... Complexity gets out of control because there are many variations that change the code. That part will be a lot harder to script.

Then there is this crucial question : what language to use ? VHDL is perfectly capable of performing the generation, as it can access files and process character strings. It's good because there would be a single language, and the generation can be performed only once in a while. However it's not the MOST appropriate language. I'd do it in JavaScript if it was easier to use on the command line... C is not a contender and I'm not keen on Python. It would be awkward in bash as well...

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