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A project log for VHDL library for gate-level verification

Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

yann-guidon-ygdesYann Guidon / YGDES 08/08/2019 at 08:550 Comments

I finally took the time to write the first code ! And I get the following LUT8s :

 and3 :    10000000
 and3a :   00001000
 and3b :   00000010
 and3c :   00000001
 ao1 :     11101010
 ao12 :    01101101
 ao13 :    11010100
 ao14 :    11010110
 ao15 :    00101001
 ao16 :    01000010
 ao17 :    10000110
 ao18 :    01001101
 ao1a :    10101110
 ao1b :    11010101
 ao1c :    01011101
 ao1d :    10101011
 ao1e :    01010111
 aoi1 :    00010101
 aoi1a :   01010001
 aoi1b :   00101010
 aoi1c :   01010100
 aoi1d :   10101000
 aoi5 :    11100111
 ax1 :     10100110
 ax1a :    01011001
 ax1b :    10101001
 ax1c :    01101010
 ax1d :    01010110
 ax1e :    10010101
 axo1 :    11100110
 axo2 :    01101110
 axo3 :    01110110
 axo5 :    10011101
 xo6 :     10111001
 axo7 :    01100111
 axoi1 :   00011001
 axoi2 :   10010001
 axoi3 :   10001001
 axoi4 :   00100110
 axoi5 :   01100010
 axoi7 :   10011000
 maj3 :    11101000
 nand3 :   01111111
 nand3a :  11110111
 nand3b :  11111101
 nor3 :    00000001
 nor3a :   00010000
 nor3b :   01000000
 nor3c :   10000000
 oa1 :     10101000
 oa1a :    10001010
 oa1b :    01010100
 oa1c :    01000101
 oai1 :    01010111
 or3 :     11111110
 or3a :    11101111
 or3b :    10111111
 or3c :    01111111
 xa1 :     00101000
 xa1a :    10000010
 xa1b :    00010100
 xa1c :    01000001
 xo1 :     10111110
 xo1a :    11101011
 xor3 :    10010110
 xnor3 :   01101001
 zor3 :    10000001
 zor3i :   01111110

The necessary source code is not as difficult as I imagined, though it requires some method. There are some obvious duplicates but it's a different problem.

All the code must be re-tested after this rewrite because I have caught a few inconsistencies...

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