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v2 in progress

A project log for VHDL library for gate-level verification

Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

yann-guidon-ygdesYann Guidon / YGDES 08/09/2019 at 20:390 Comments

It was not easy but i have a first proof of concept for the code !

https://cdn.hackaday.io/files/1625946956421696/A3Ptiles_v2pre20190809.tgz

It is far from being the most elegant or efficient but it works. A 2-stages compilation system creates the whole collection of gates and their definitions, the result is provided in the archive in case you can't run the generation script.

It covers the alteration of a given bit of the lookup table of a given gate. The access works with a number system: the program lists all the alterable gates and provides their path along with an index, that is reused to address the gate. It should be pretty easy to use in a script.

The delay system should also be redesigned. Probably with real data from the datasheets, though this is pointless without information about the routing delays...

The sequential gates are missing too, and the smaller gates are still absent...

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