I've redesigned the algorithm that explores/registers the depth of all the gates and outputs and the result is pretty good :

  ************ FIXING DEPTHLIST ************
 ----- Depth=1
   > registering Gate #1
   > registering Gate #2
   > registering Gate #3
   > registering Gate #4
   > registering Gate #6
   > registering Gate #8
 ----- Depth=2
 found Output #0
 found Output #1
 found Output #2
   > registering Gate #5
   > registering Gate #7
   > registering Gate #10
   > registering Gate #9
   > registering Gate #11
 ----- Depth=3
 found Output #3
 found Output #4
   > registering Gate #12
   > registering Gate #13
 found Output #5
 found Output #6
 ----- Depth=4
 found Output #8
 found Output #7
 DepthList : fixed

The last version suffered a few small issues that became real problem when I tried to add "loop detection" (such as a flip-flop made of cross-interlocking gates).

The new algorithm uses a different approach, where a gate is re-added to the "to-scan list" when all its inputs have been scanned already, and have a definite "depth".

A counter for every gate is initialised with the gate's number of inputs and it is decremented each time an input is registered.

At the end, if the counter is not zero, then gate has a missing input (or a bug).

There is the special case of the VCC/GND gates with no input... but they shouldn't be used in ASICs, right ?

The nice thing about the new approach is that I merged it with a new 2D gatelist that is organised with the depth, respective to the input, so it's easier to display the circuit.