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A project log for VHDL library for gate-level verification

Collection of ASIC cells and ProASIC3 "tiles" in VHDL so I can design and verify optimised code without the proprietary libraries

yann-guidon-ygdesYann Guidon / YGDES 03/24/2020 at 17:290 Comments

I think I skipped v2.7 that was on the drawing board (I still need to make more examples), but v2.8 is here !

A3Ptiles_v2.8_20200324.tgz

It adds (or restores) a feature/behaviour that was considered in the beginning, then abandoned, then lately I thought it would be cool

  1. to be able to simulate the designs at a slightly faster speed (though it's subjective)
  2. to be able to synthesise the designs on different platforms that don't understand/know Actel's legacy conventions.

The last point convinced me so here it is : PA3_definitions_simple_nodelay.vhdl

I copy-pasted the code that generates the LUTs. I had to modify the code of the MX2x gates and this also introduces a timing inconsistency but it's minor and not used (since it's apparent only when timing is used AND I'm NANDifying my code).

This version doesn't use external definitions that are necessary for analysis and introspection. It's purely so the Actelified source code can work on Lattice/Xilinx/Intel/etc.

The default version remains the "trace" one, and it can be regenerated at will, with the timing you want, since I have provided 2 scripts and the generator can be rerun as you like.


Update 2020028 : both versions are built now by a single script so they can be used in parallel, selected by the -P (include path) parameter of GHDL.

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