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8 Bit Breadboard CPU

A home-brew 8 bit Microprocessor built on a breadboard
64K Address Space, IRQ, and DMA
16 Bit Stack Pointer, 4 8 bit Registers or 2 16 bit

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This will be an 8 bit CPU built to interface with a RAM, ROM, and I/O. It will be built out of standard TTL logic on solderless breadboards.

CPU Includes (current design):
- 64K address space (16 address lines).
-Two 16 bit Registers that can be used as 4 8 bit registers.
- 16 bit program counter.
- 16 bit stack pointer.
- 8 bit status register, high nibble used as instruction step counter (carry, zero, equal and negative)
- 8 bit Instruction register (256 possible opcodes)
- IRQ input
- DMA input
- Reset input
- Tri-state address and data line buffers
- AB, XY, PC, SP, and instruction step counter built out of up/down counters for quick incr / decr.

I was doing research for a new hobby project.  I wanted to build a 68000 system on a bread board with I/O and possible video.  As I dug deeper I started shifting towards maybe starting with an 8 bit CPU (6809) and then do the 68000 after.  I'm pretty rusty at hardware, haven't done anything serious since the early 90's.  

While doing this research I discovered a brilliant You-tuber named Ben Eater https://www.youtube.com/channel/UCS0N5baNlQWJCUrhCEo8WlA . He is an excellent presenter and educator.  I watched his series on building an 8 bit bread board computer.  He goes through step by step building a functioning 8 bit computer out of TTL logic.  I'm sure many of you might be familiar with his work.

I've never really had a good understanding of the internals of a CPU.  I knew that it involved state machines and registers but didn't really grasp how it functioned.  In his series he broke down the computer into easy to understand blocks.  After watching his series I was inspired to try and build something of my own.

Instead of building a simple computer, I want to build a self contained CPU that could be connected to a complete system (RAM, ROM, and I/O).  I will use RAM and some I/O to build it but  design it so it can be separated. I want to have some more advanced features on my CPU while trying to avoid feature creep.  I do want to actually finish.

I've ordered a bunch of Breadboards TTL chips, resistors, LED's, DIP Switches, EEPROM's, RAM chips, hookup wire (8 colours), capacitors, 555 timers, toggle switches, and some other bits.   I found a good deal on the long (63 row) breadboards on amazon.  3 boards for $12CDN with free shipping.  I just received 9 of them today and they are superb quality.

I can't wait to get the rest of the supplies so I can start tinkering.

I've drawn up a block diagram for the basic design. 

https://docs.google.com/drawings/d/1BW84zwO5effvYcdKjxzyki9cuvuHsM98z6nAamw4iTM/edit?usp=sharing

I've also started an instruction list which also has a page that lists the full names for all the control lines shown in the block diagram.  Like I said I'm pretty rusty and not up to speed on normal naming conventions.

https://docs.google.com/spreadsheets/d/1kbxYGDeIOszgvjPYRdes-bELOBlojT_tjxe_RD9MVUQ/edit?usp=sharing

I've started an upverter project where I will be posting all the schematics.

Idea's and advice are most welcome.

  • Combining Modules

    2-Zons5 hours ago 2 comments

    I've been working on combining the modules I have so far.  It's been I little trickier than I'd hoped but It's coming along.  I built a temporary data and address bus driver with LED readout.  In my initial testing I just had the dip switches connected to the data inputs of the modules.  This wouldn't let me test the modules output to the bus.  So by separating the dip switches with their own bus driver I can now test what the modules put out on the data bus.  I did the same with the address bus.  I'w worried that all these dip switches are going to draw too much current though.  I think if I make a front panel for the system I will use toggle switches that simply switch between VCC and GND.

    On another note.  Upverter sent me an email.  They chose my project for a case study.  They want to help me get it manufactured (PCB and components). 

  • Status Register

    2-Zons3 days ago 0 comments

    Finished this last night.  This was more difficult than I expected.  It's only a 4 bit register but it took quite a bit of translation from logisim to reality, trying to keep the chip count low and minimize unnecessary gate delays.  My satus register (SR) has 4 flags: Equal EQ, negative NE, zero ZE, and carry CA.  SR is set by the ALU during any ALU operation.  It can also be set by loading a value from the data bus.  The CA flag will affect subtraction or addition in the ALU.  All 4 are used by the instruction decoder for conditional jumps.  The SR can also be sent out to the data bus for saving it on the stack or for logical functions in the ALU.  I was able to get by using only two 2 way bus driver IC's.  One for both in from, and out to the data bus, and the other for buffering the flag outputs of the ALU.  This is what made it tricky to make sure that the internal bus in the SR would never have more than one source based on the control signals: FL-O, Flags out to data bus; FL-I, flags in from data bus; and FL-O, store flags from ALU (an operation is taking place).

    In the block diagram and in logisim SR is an 8 bit register, the first 4 bits being the instruction step counter.  Since each 4 bits needs it's own IC (a counter and a D-flip flop), and they work completely independently of each other I will move the step counter to the same location as the instruction decoder.  Keep the wire runs shorter.  The step counter is never loaded from or sent to the data bus.

    I've got enough modules completed to start fitting them together.  Which is what I'm working on now

  • AB Register

    2-Zons4 days ago 1 comment

    Finished the AB register.  It's the same as the XY register minus 16 bit in and out to address bus.  I'm getting much better at the wiring.  For previous modules I would wire up just enough that I could test it, and then add  a bit at a time testing as I went.  This time I wired up the entire thing before testing, and only had one mistake when I fired it up (two bits crossed over on A).  It was a quick to spot and quick to fix.  My productivity should go up now.  I've also received all of my orders so I have everything I need to complete the entire system.  I dug up my label maker to tag the control lines.

    I'm getting enough modules complete to start wiring them all together.  I can better judge now how many boards it will take for the whole system.   I wish I could buy the power rails separately.  I will be needing quite a few for data and address bus.

  • ALU

    2-Zons6 days ago 1 comment

    ALU is mostly complete and working.  Using 2 x LS181's.  Top right LED's show contents of input register tied to input B on 181's.  Databus (Dipswitches) tied to input A.  Blue LED is  carry not.  Bottom Right LED's show contents of output register.  Showing A XOR B.  All loopy wires are temporary for testing, as well as the 5 dipswitches on the board, they will be control signals when hooked up to the bus.  Only need to implement zero, negative, and equal flags.  I hope I can use the A=B output on the 181's and'ed but when I tested it in logisim it didn't work properly.  I haven't tested on this setup yet.

  • Completed and Rebuilt XY Register

    2-Zons01/12/2019 at 04:32 0 comments

    Complete XY Register

    I started over and completely rebuilt the XY register.  I was having trouble with the bus drivers.  I switched to 74HC245's from 74ACT241N's.  The 241's were  actually dual 4 bit buffers each with their own enable line (one active hi and one active lo).  The enable lines couldn't be tied together and each 4 bits was output on opposite sides of the chip which made wiring really messy.  I also got new wire delivered which is the same guage (22AWG) but has a thinner insulator and is much nicer to work with.  I've tested out all the functions and they all work:  X inc and dec; Y inc and dec; XY inc and dec; load XY from address bus; load X or Y from data bus; push X or Y to databus; push XY to address bus; and reset.  Only thing left is some control signal logic which I am missing some OR gates to complete.  I neglected to order them earlier.  I think I'll build the ALU next.

  • XY Register

    2-Zons01/08/2019 at 04:37 4 comments

    Working on the XY register.  This is the register with the most control signals and features.  Separate hi, lo byte, and word increment and decrement.  Hi or lo byte in from or out to databus.  Word in from or out to Address bus (Address bus is used for 16 bit register to register transfers).   The address bus side of in and out is finished and tested.  Need to wire data bus in and out and lo byte to hi byte up down logic.  I've already used over 40' of wire just for this one register.  I'm going to need a lot more.  The yellow loops are control signals tied hi or lo for testing.  Dip switches are acting as the address bus.

  • Construction has started

    2-Zons01/06/2019 at 00:18 3 comments

    Finally received the delivery I was waiting for to start building something.  This is the clock circuit.  It's pretty much an exact copy of Ben Eater's 8 bit computer clock.  Starting from the left: A 555 circuit to generate and adjustable square wave clock that can run as slow as 0.5 Hz.  Second, another 555 circuit to debounce a pulse that will be fed into the output logic for single stepping.  Third, a final 555 circuit to debounce the enable circuit that feeds into the output logic to select from the single step or clock.  Red button is single step pulse, beside the toggle for the select.  Next are two quad nand 7437 for the output logic.  Second chip is not used yet.  Will be used to generate inverse clock, and halt for DMA.

    No need to comment on the crappy soldering job on my power input.

  • Debugged Logisim Design

    2-Zons01/01/2019 at 20:02 0 comments

    Added enough instructions to test out all the component designs.  Found a bunch of bugs and fixed them.  Learned a heck of a lot.  Came up with some changes to the overall design, like having a control line to load the data-bus with zero's.  This will save many cycles for certain instructions and allow for a CLR instruction.  Before adding the zero control it took several cycles for an instruction to clear anything by XOR'ing it with itself in the ALU.  

    Another design change is the ability to transfer 16 bits in one cycle through the address bus, between registers.  Currently it's only implemented with AR, being able to store what is on the address-bus.  AR is an internal register not available to the programmer, used for holding addresses.  Without it there would be no way for an instruction to load the PC from memory without changing the state of another register.  In logisim all my 16 bit registers are copies of the same sub circuit so implementing 16 bit loads into other registers would be easy.  I will need to do an analysis of my currently planned instruction set to see which registers could use it.

    If anyone is interested in my files let me know and I'll upload them.

  • Logisim model working

    2-Zons12/29/2018 at 01:55 0 comments

    I've don'e it.  I've got my completed CPU design running in Logisim.  Very handy tool indeed.  I would be interested to know if the simulators in FPGA editors have some of the functionality of Logisim.  Specifically, being able to edit and load RAM and ROM images.  

    I haven't programmed all the microcode into it yet, so haven't been able to ensure there are no design bugs.  I have programmed a complete reset instruction that should work for hard and soft reset.  It loads SP and PC from address $0000 and $0002. It doesn't clear any of the registers besides A, SP, SR and PC.  The ZR flag is left set after it is finished.  My plan for IRQ is that it will grab the IRQ vector from address $0004 after it pushes the SR and PC.  It will be up the the IRQ routine to save SR, AB, or XY if required.

    Now I just need to program a few more instruction in to fully test all areas of design.  Still waiting for some more parts to start the actual build.

  • Building my Design in Logisim

    2-Zons12/26/2018 at 07:36 0 comments

    We'll I've been busy working out more details of my design in Logisim.  I was finding it very helpful to think through my design by building the schematics in Upverter.  I was working on the instruction decoder and was finding myself needing to figure out some logic.  I was scribbling on paper to try and work it out when I thought I'd try and use Logisim.  I had never used it before and didn't really want to learn another piece of software.  

    Wow,  I'm sure glad I did.  What a nice little program it is.  I should have listened to @roelh 's advice to begin with.  It's been really helpful in working out the details of the design.  It doesn't have a library of standard IC's so I started my own library of the chips I'm using.  I used the schematics from datasheets.  I put in Schematics for for the 181 ALU and the  193 up/down counter that I'm using for my registers.  Logisim does have an up/down counter in it's library but I built them from the schematics so I would hopefully simulate the same behavior.  

    I'm getting close to finishing the whole design.  I still haven't received all of the components I need to start building on breadboard, but maybe it's not such a bad thing to be forced to do only planning before actually wiring anything. 

    I'll add a screen shot of the main circuit.  If anyone's interested in the files let me know.

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Mario wrote 01/11/2019 at 02:27 point

Nice and educative work! By adding TTL Analog to Digital Conversion (ADC) IC at the input and implementing DSP algorithms using e.g. fixed-point arithmetic (execute calculations with real numbers using integer arithmetic circuits) it might be possible to implement even DSP processors in TTL logic.

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Peabody1929 wrote 12/11/2018 at 17:34 point

Do you have a goal for the instruction cycle time?  This could be the clock rate times the number of clocks it takes to execute an instruction.

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2-Zons wrote 12/11/2018 at 22:36 point

I have a 16 step instruction counter, so the max instruction will take is 16 cycles.  I have a control line to reset it so I will be able to program each instruction to take the minimum amount of cycles.  I haven't started the microcode yet but from what I'm thinking most 8 bit instructions will take 3 cycles.

As for the frequency of the clock:  I will build a 555 circuit with a pot for initial construction.  Nothing too fast, probably max about 50Khz.  My plan is that once I've got the design to a certain point I will write a program to test every instruction and then see how fast i can get it to run without errors.  I've got 20MHz crystals, if it handles that I would get faster ones.  I would be happy If I could get it running at 10Mhz, but I'm totally new at this.  We will see. 

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Steve Toner wrote 12/08/2018 at 01:00 point

OK, just glancing at the register schematic, I see a couple of issues:

1. I wouldn't drive an LED directly from the output of an LS chip.  There should be a current-limiting resistor in there.  Don't depend on the output resistance of the chip itself.  Because a TTL chip can sink more current than it can source, you typically pull the cathode of the LED down rather than trying to pull the anode up.  CMOS is different, and can typically source and sink (approximately) equal amounts of current.

2. You can't reliably drive an HC chip from an LS chip, especially if there's an LED pulling down the output level of the LS chip.  HC series expect a higher input voltage to indicate a logic '1'

3. Pullup resistors: typically a current-limiting resistor is used when pulling a pin to logic level '1' rather than connecting it directly to Vcc.  There are people who will tell you it's OK to connect a CMOS input directly to Vcc, buut it doesn't hurt to include it.  And if someone somewhere down the line might substitute a TTL chip for the CMOS part, then it is most certainly a good idea to include it.

4. U76A: Don't leave the unused inputs floating.  Ground 'em.

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2-Zons wrote 12/08/2018 at 01:09 point

Thank you for the info.  These are the chips I have.  What would you recommend to interface the HC with LS?  I can go through my inventory and see what other HC I have, but I think I got the HC because I couldn't source the LS.  I will have go through my parts list again.

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Steve Toner wrote 12/08/2018 at 01:55 point

You would typically use a pullup resistor on the LS output/HC input.  However, with the LED there you're still going to have problems.  Say it's a red LED that has a forward voltage of 2V.  The way the circuit is drawn (with the input of the HC chip connected directly to the anode of the LED), the HC chip is going to see 2V at its input even with a pullup resistor in there.  And it needs something like 3.5V.  If you were to drive an HC chip directly from an LS chip so that the HC is the only load (i.e., no LED), you'd probably be OK because the HC input draws minimal current so won't pull the nominal 5V output level down...

HCT parts are TTL compatible.  But the LEDs may still cause problems if they are not buffered.

Additional reading:

http://www.ti.com/lit/an/scla011/scla011.pdf

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roelh wrote 12/08/2018 at 22:15 point

I agree with Steve. LS parts can not deliver much current in high state. You could however use low-current LEDs that light up below 1 mA, the series resistor can then be something like 2K2. 

For the part that receives this logic signal, you could use a HCT instead of HC part. A HCT will see a logic high when the voltage is above approx. 2.4 volt.

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Yann Guidon / YGDES wrote 12/07/2018 at 01:26 point

For PC and SP, you might like https://hackaday.io/project/8121-discrete-yasep/log/27843-the-registers
This system uses cascaded 74'193 up/down counters for several registers, which would help keep your system simple.

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Yann Guidon / YGDES wrote 12/07/2018 at 01:31 point

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Paulo Constantino wrote 12/06/2018 at 19:58 point

why did I receive an email saying you mentioned my name ?

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2-Zons wrote 12/06/2018 at 23:08 point

Not sure.  I didn't mention you, should I have?

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Yann Guidon / YGDES wrote 12/07/2018 at 01:21 point

the site's server has some hicups...

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roelh wrote 12/06/2018 at 12:40 point

Hi Martin,

nice to see another homebuilt cpu here !

I do have a few questions and some advice....

- I do not see logic instructions (AND, OR, XOR) in your ALU. Will you add them ?

- Do you have ideas about the instruction set that you will implement ?

- I suppose you will have a microcoded control. You have a lot of control signals, 48 total in your list. I suppose the microcode will be smaller than that, and the microcode will go to a few decoders to produce the control signals ?
  My experience is, that a datapath with registers and ALU is in most cases not so hard to design. The complexity comes when you want to control the whole stuff. 

- Your design for the 16-bit register seems much too complex for what it does, having 11 IC's, while it could be done with only two 74HC574 (with some loss of functionality).  Incrementing would be useful for PC, and inc/dec for SP. Allowing only 16 bit inc/dec (so dropping 8 bit inc/dec) for these will already simplify your register. For SP, you could consider the simplification to have the upper byte fixed, as in the 6502.

- For registers other than PC or SP, you can consider doing inc/dec with the ALU, in order to simplify these registers.

- It seems that your internal databus is 8 bit wide and the ALU 16 bit wide. I would suggest to make them the same size, 8 bit would be enough for a first design.

- I would suggest that you first build a software model of your processor (or a Logisim version), and make a few programs for it. That will show if things are missing, and will show if there are unused features.

For inspiration you could also look at the gigatron (https://hackaday.io/project/20781-gigatron-ttl-microcomputer) or my design for an ALU (https://hackaday.io/project/160506-4-bit-ttl-alu) and for the simplest TTL CPU ever designed (https://hackaday.io/project/161251-1-square-inch-ttl-cpu).

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Dave's Dev Lab wrote 12/06/2018 at 18:35 point

@roelh - oh oh oh, my feelings are sooo hurt! you didn't include my stuff! hehe

https://hackaday.io/project/158510-ddl4-cpu

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roelh wrote 12/06/2018 at 19:36 point

Sorry Dave !

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2-Zons wrote 12/06/2018 at 18:48 point

@roelh  Thanks for the feedback.

1 - I wasn't planning on having anything but add / subtract in the ALU.  I haven't really wrapped my head around an ALU with more functions.  I know how to implement the add / sub with zero, carry, and negative status.  I looked at your ALU design, and it seems quite simple for all those functions.   If I can wrap my head around how it works I might try and implement it, that might mean more control lines however, but they would be exclusionary so it might be OK (see 3).

2 - If you look at the other page of that google docs spread sheet you will see a list of instructions that I have come up with, based on the control lines I have, that I can think of.  If I missed any, I would like to know.

3 - As for the microcode.  I plan on using EEPROM's to decode.  You are correct with the 48 lines.  I am simplifying the logic by considering exclusionary groups (see spreadsheet).  E.g. all the data out controls.  Only one of those control lines can be used at a time.  There are 12 of them.  So I can use 4 bits of combinational logic output that will drive a 4 bit mux to get up to 16 exclusionary control lines.  There are only 4 address out controls so I will use a 2 bit mux for those.  Total reduction of 10 bits (2 less ROM chips).  If you can think of other obvious ways I could reduce the control logic that would be awesome.

4 - I don't mind the complexity of the registers.  The SP, and PC will be a lot simpler because they won't have any logic for isolating the inc/dec of the individual bytes.  They will also be only inc and dec respectively. having incrementing registers will make the code much more efficient IMHO.  Having it in the register will allow it to be done in one cycle and added to load / store instructions with no extra cycles.  Having a register auto increment /decrement every time it is used as a pointer without extra cycles is a huge for software efficiency IMHO.  As for an 8 bit SP: I've always thought that a 256 byte stack is too limiting for software.  Probably the only problem I have with the 6502, I know I'm not the only one.   Also with my register / instruction design B and Y are selectable page pointers, setting the page with A or X.  I guess I'm a software guy at heart, and I don't mind making the hardware more complex if it makes for simpler more efficient code.

5 -Inc / dec in the ALU.. see 3 and 4.

6. Having an 8 bit ALU would be less chips, slightly more complex IMHO.  It might even be the same amount of chips.  I might design both and see. 

7. Although I do like the idea of running a sim of my design, personally I think it will be easier to test on the actual circuitry.  I will build each block (AB, ALU,XY, etc) on it's own bread board, starting with a clock circuit that can be paused and single step.  Then a register, Then the ALU etc.  Using LED's I can even test parts of each block. I might be wrong but to me this feels easier.  

8. I was aware of the gigatron (one of the inspirations for this project).  Thanks for the links to your ALU design.  I was writing this response point by point and then saw your link.  Had to change my response to your ALU question.  I was originally saying if I could see a design for an ALU with more functions. That square inch CPU is insane.  I think it's a good example of, if you simplify something too much it makes it can make it more complex in some ways.   

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roelh wrote 12/06/2018 at 19:34 point

Thanks for your explanations. I overlooked the instruction tab in your spreadsheet. It does however not show addressing modes for the instructions. For instance, will ADD add from a memory address, from an immediate, or from another register ? 

I do not know a single CPU (except the square inch cpu) that has no logic operations. At least a NAND or NOR should be present I think, since other logic connectives can be derived from that.

Having inc/dec capability will indeed win you a few cycles, but that will be of limited use when the other parts of the cpu are not optimized for speed.

Maybe my own focus is too much toward lowest component count solutions....

The square inch cpu is indeed not very fast or practical, but I think not much has to be added to make it useful.

And before I get a complaint from @Yann Guidon / YGDES  that he is not mentioned, you might find his Processor Design Principles a good read: https://hackaday.io/project/46000-pdp-processor-design-principles

There are even famous processor designs named after this: PDP-8, PDP-11 !

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Yann Guidon / YGDES wrote 12/06/2018 at 19:46 point

@roelh  me ? complain ? come on, never ever !!! :-P

I'm looking with interest (like all the CPU projects here) and wait for the perfect timing to invite our new friend to #Hackaday TTLers 

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