I've don'e it. I've got my completed CPU design running in Logisim. Very handy tool indeed. I would be interested to know if the simulators in FPGA editors have some of the functionality of Logisim. Specifically, being able to edit and load RAM and ROM images.
I haven't programmed all the microcode into it yet, so haven't been able to ensure there are no design bugs. I have programmed a complete reset instruction that should work for hard and soft reset. It loads SP and PC from address $0000 and $0002. It doesn't clear any of the registers besides A, SP, SR and PC. The ZR flag is left set after it is finished. My plan for IRQ is that it will grab the IRQ vector from address $0004 after it pushes the SR and PC. It will be up the the IRQ routine to save SR, AB, or XY if required.
Now I just need to program a few more instruction in to fully test all areas of design. Still waiting for some more parts to start the actual build.