Added enough instructions to test out all the component designs. Found a bunch of bugs and fixed them. Learned a heck of a lot. Came up with some changes to the overall design, like having a control line to load the data-bus with zero's. This will save many cycles for certain instructions and allow for a CLR instruction. Before adding the zero control it took several cycles for an instruction to clear anything by XOR'ing it with itself in the ALU.
Another design change is the ability to transfer 16 bits in one cycle through the address bus, between registers. Currently it's only implemented with AR, being able to store what is on the address-bus. AR is an internal register not available to the programmer, used for holding addresses. Without it there would be no way for an instruction to load the PC from memory without changing the state of another register. In logisim all my 16 bit registers are copies of the same sub circuit so implementing 16 bit loads into other registers would be easy. I will need to do an analysis of my currently planned instruction set to see which registers could use it.
If anyone is interested in my files let me know and I'll upload them.