Finished this last night. This was more difficult than I expected. It's only a 4 bit register but it took quite a bit of translation from logisim to reality, trying to keep the chip count low and minimize unnecessary gate delays. My satus register (SR) has 4 flags: Equal EQ, negative NE, zero ZE, and carry CA. SR is set by the ALU during any ALU operation. It can also be set by loading a value from the data bus. The CA flag will affect subtraction or addition in the ALU. All 4 are used by the instruction decoder for conditional jumps. The SR can also be sent out to the data bus for saving it on the stack or for logical functions in the ALU. I was able to get by using only two 2 way bus driver IC's. One for both in from, and out to the data bus, and the other for buffering the flag outputs of the ALU. This is what made it tricky to make sure that the internal bus in the SR would never have more than one source based on the control signals: FL-O, Flags out to data bus; FL-I, flags in from data bus; and FL-O, store flags from ALU (an operation is taking place).
In the block diagram and in logisim SR is an 8 bit register, the first 4 bits being the instruction step counter. Since each 4 bits needs it's own IC (a counter and a D-flip flop), and they work completely independently of each other I will move the step counter to the same location as the instruction decoder. Keep the wire runs shorter. The step counter is never loaded from or sent to the data bus.
I've got enough modules completed to start fitting them together. Which is what I'm working on now