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Lion FPGA CPU/Computer

A 16-bit FPGA CPU I call Lion CPU and a computer, the Lion computer. Everything built from scratch.

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I started to explore FPGAs and made a CPU, then when I realized that it really works I set a goal to make a computer like the early 80's home computers I used as a kid and I think I did it.

I built a video controller, a UART, wrote an assembler and ported PA Tiny Basic adding fixed point and more. It started to feel like a home computer. I added SPI to use a SD Card and wrote simple FAT system support. For sound I made two audio channels and a noise channel.
Then I added hardware sprites.
I made a generator for Lion CPU code for the Java Grinder open source project and so I have a simple Java Compiler for Lion. Then I wrote a simple demo game in Java. Of course I have added joystick port.
I added a second video mode 16 colors and 45 multi-color sprites.
Last addition is Cpu support for 8 pages of 64K (512K total).
Manos wrote a nice windows emulator of Lion in C#.
Still more to do in hardware and software but it already is a working computer.
Leon (Theodoulos Liontaki

Current Specs

CPU : Lion 16bit  @50Mhz

Memory:  8K rom + 56K ram + 32K video ram + 12K sprites ram + 64K paged ram

                support for up to 512K total ram in 64K pages

Video Mode 0 (text optimized):  640x240 pixels, 30x80 chars, 16 colors (2 per char)

Video Mode 1 (graphics optimized):  320x200 pixels, 25x53 chars, 16 colors

Sprites: 45 hardware sprites, 15 colors + transparency, 16x16 pixels, double buffered.

Storage: basic FAT support in SD card 30Mbytes

Sound: 3 channels + 1 noise channel, 8 bit digital volume control

Ports:   2x joystick, 1x Serial, 1x VGA, 1x PS/2 keyboard

Software: Assembler, Palo Alto Tiny Basic (with fixed point arithmetic),

                 Java Grinder Compiler (with floating point support), Astro java game.

And a Lion Windows emulator written by Manos in C# see github project link.

Source code available at github (CPU+system VHDL/schematic, assembler, Rom+TBasic assembly)

More information and assembly description at my website (first project page).


  • 1 × Cyclone V 5CEFA2F23I7 board
  • 1 × SD Card board with SPI interface
  • 1 × Power supply 12V dc 15W (for LCD) or 5V (without LCD support)
  • 1 × TTL to USB Serial board
  • 1 × LCD controller with vga input (Optional)

View all 7 components

  • Lion got vector graphics too!

    Leon21 hours ago 0 comments

    Added a vector graphics controller in the fpga with 2K dedicated ram for vector end points.

    Currently works with the TLC7226IN 4 channel 8bit DAC chip.

    It produces the x,y,z output signals that I feed in my recently acquired HP-1330A X-Y Display Monitor.

    I implemented the Bresenham's line algorithm in the fpga to draw a line from the previous drawn point to the last one.

    Soon I'll have a video demo of the Astro game in vector graphics!

    Raster and Vector graphics are totally independent and can display concurrently.

    The following picture was taken before implementing the line draw algorithm:

  • Sound

    Leon09/08/2019 at 17:30 0 comments

    Sound capabilities are not advanced in Lion but...

    I increased the sound channels to 3 and added 255 step 8bit digital volume control for each one.

    A channel outputs a square wave signal with frequency  obtained by dividing 200khz by a 13bit number.

    A channel can be mixed with the white noise (lfsr) channel, noise comes with a frequency bandwidth limit.

    Every channel can be enabled with 8 different duration values 2sec, 1sec, 0.5 sec,  ....

    Status of any channel is available to determine if it has finished playing the previous note in order to send it a new note but a channel can be interrupted any time to start a new note.

  • Cyclone V FPGA

    Leon09/07/2019 at 09:58 0 comments

    Moved the project to Cyclone V FPGA 5CEFA2F23I7, now I don't use an external static ram chip because this FPGA has enough internal ram for Lion's 128K ram + 32K Video ram + 12K sprite ram. It also has plenty IO pins for new features and it's logic elements are faster.

  • PS/2 keyboard controller

    Leon07/14/2019 at 23:30 0 comments

    At last I wrote a controller for PS/2 keyboard in the fpga. It has a 16 key queue.

    I was postponing it and was using an external board instead, but once I started, it was easy and fun.

  • Memory block transfers

    Leon07/06/2019 at 14:52 0 comments

    I keep adding instructions that i think are useful or add speed as long as unused opcodes are available.

    I added ram block transfer commands. The IDX register that was used as a loop counter and index, is used by the transfer instructions to hold the number of words to be moved.
    Instructions MTOM, MTOI, ITOM, ITOI with two arguments An1,An2 move fast blocks of words starting from memory or IO address An2 to memory or IO address An1.

    Instructions NTOM, NTOI with arguments An1,N or An1,An2 fill the block pointed by An1 of size IDX+1 with the 16 bit value N (or An2).

        MOV A1,buffer1
        MOV A2,buffer2
        SETX 99
        MTOM A1,A2  ;copy the 100 words block starting at buffer2 to buffer1
        SETX 99
        NTOM A2,0   ;fill buffer2 with zeros

    These new instructions drastically improved scrolling routines speed

  • Memory Pages in Lion

    Leon06/28/2019 at 13:53 0 comments

    When I first started to design the cpu I thought that 16bit address bus is ok for a homebrew cpu but after I made the Lion computer 64K rom+ram seemed very small although it used separate video and sprites ram. I wanted more memory and the more convenient way to do it is using pages. So I added 3 more address pins to lion cpu and added the necessary commands to support 8x64K pages.


    The SR register was extended from 8 to 16 bits and now the 9 most significant bits bit15 to bit7 hold the current code (bit15-bit13), data (bit12-bit10) and stack page (bit9-bit7).

    Instruction SDP sets the current data page, SSP sets the current stack page

    PJMP jumps to another address/code page.  PJSR jumps to a subroutine to another address/page and PRET returns.

    Also another register named OtherDataPage ODP assists in data transfers between pages by holding a source or target page for use with instructions PMOV PMOV.B

    Interrupt routines always use page 0 as a code page.

    I'm currently testing the functionality of this implementation and need to make more changes to the assembler

  • Keyboard

    Leon05/24/2019 at 16:49 0 comments

    Fixed some issues with the keyboard, now Shift and Caps Lock work well, although I cannot turn the Caps led on due to the external controller board I use limitations. Maybe I have to build my own as i did with everything else although I find it not so interesting.

  • Upgraded text mode 0

    Leon01/08/2019 at 15:17 0 comments

    Since I made a second video mode for graphics and added more vram I used the extra ram to also upgrade the first video mode for text so its now 640x240 pixels and with a 8x8 font can display 30x80 characters in two colors per character from 16 available.

  • Second sprite controller

    Leon01/03/2019 at 16:19 0 comments

    Added a second parallel sprite engine so now 28 sprites are available for mode 1 in 8k sprite ram. It is synchronized using the vertical synch signal with the video controller that generates the first 14 sprites. Sprite ram is now split in two 4k independently addressed units so each sprite controller has its own ram. Sprite ram is mapped in I/O space at address 16384.

    I can any time easily add one or two more sprite controllers to have 42 or 56 sprites.

  • 16 sprites

    Leon01/02/2019 at 21:54 0 comments

    Number of mode 1 sprites increased from 10 to 16.

View all 12 project logs

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Discussions

Dusan Petrovic wrote 03/25/2019 at 12:32 point

This project is a great addition to the #Homebrew CPU list. Thanks Leon!

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Leon wrote 03/25/2019 at 19:09 point

thank you

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f4hdk wrote 03/24/2019 at 14:37 point

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Leon wrote 03/25/2019 at 01:18 point

thanks for the tip

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Goran Mahovlic wrote 01/08/2019 at 10:15 point

It would be great to see your console on our FPGA :) http://radiona.org/ulx3s/

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Leon wrote 01/08/2019 at 14:59 point

Nice board!

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Goran Mahovlic wrote 01/08/2019 at 22:43 point

Tnx, it was made for university in Zagreb(Croatia), and at some point we will try to push it to market.

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Leon wrote 01/08/2019 at 00:56 point

thank you Goran

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Goran Mahovlic wrote 01/07/2019 at 14:45 point

Great work!!!

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