The first module I built for this project was the clock. With the exception of some LEDs, I have followed Ben's clock design as closely as possible. There are three 555 timers, set up as astable, monostable and bistable timers. The astable timer is used for the regular clock pulse, the monostable timer is for a manually triggered lock pulse and the bistable timer is used to select between the free-running timer or the manually triggered pulse. The logic chips (74LS04 Hex Inverter, 74LS08 Quad And, and 74LS32 Quad Or) are used to combine the signals from the three 555 timers, plus a HALT signal (the red fly lead just right of centre in the picture below) to generate the final clock signal. A schematic for this clock can be found on Ben's site. (Note: For this project, I will not be including circuit diagrams, instead I will link the Ben's site where he has diagrams and links to all his YouTube videos.)
The only real modification here is the inclusion of several indicator LEDs, so I can see what is happening. (Plus I love blinkenlights!) The green and yellow LEDs above the switch indicate whether the clock is in free-run mode (green) or manual trigger (yellow). The yellow LEDs on the bottom rail just show the output of the two clock timers.
While I think the module is a bit too complex for what it is supposed to be, I can understand that Ben is not designing an optimal CPU, rather he is using this as a way to teach people about 555 timers and logic circuits. I have already (half) designed a new clock for my next CPU project, and this clock will be much simpler, containing only a single 555 timer. I will push the handling of the HALT signal to the CPU-proper, so the clock will be just a clock - no complex logic dealing with combining signals, inverting signals or handling HALT states. My v2 clock will be as simple as possible.