The details for this project are going to be in the build logs, each detailing one experiment on the way to ... well, to be honest, I'm not entirely sure yet.
A project in which I try to go faster and faster
The details for this project are going to be in the build logs, each detailing one experiment on the way to ... well, to be honest, I'm not entirely sure yet.
Portable Network Graphics (PNG) - 88.77 kB - 06/01/2019 at 11:31
JPEG Image - 3.19 MB - 05/02/2019 at 17:53
I send out another batch of 2-layer PCBs to test different coplanar waveguide geometries and SMA end-launch connector footprints. There are seven different CPWG widths and seven different footprints on the PCB. I populated one with $0.20 ebay SMA connectors for the first test. I'll compare with $2 name-brand connectors next, then maybe some good ones.
It took two tries to make the boards this time because of sloppiness and an Eagle bug. When you copy a single via in Eagle, you get another one on the same net. When you copy more than one via at once, they all end up on another net, for instance GND1, GND2, etc, which aren't connected to anything. I quickly cut & pasted the stitching vias on either side of the CPWG traces, and didn't notice this before sending out the first batch of boards. This PCB was too simple to bother running DRC, which would have caught it right away :-(
Here are the measurements, summed up in an animated GIF. This format really shows how the impedance changes with the trace parameters. In this case, I kept the CPWG gap fixed at 6 mil, and varied the trace width. A common geometry for 50-Ohm CPWG on 2-layer 62-mil PCBs is 32/6, a 32-mil wide trace with 6 mil gaps on either side. I found that when covered with soldermask, the characteristic impedance of such a trace is typically too low - a narrower trace is called for.
The upper cursor is at 50.91 Ohms, and the lower at 49.3 Ohms. The long flat area is the CPWG trace, and you can see the impedance increase as the trace width is reduced. The best match to 50 Ohms is between 30 and 31 mils. 30.5 might be a good width to use. Of course, this is going to vary because of the somewhat random dielectric constant of FR-4, but at least it's a real data point.
The other variable in this test is the shape of the SMA connector footprint. The footprint consists of a 40-mil wide pad to solder the SMA connector pin to, with gaps on either side. Because the pin and the connecting solder introduce capacitance to the structure, you have to widen the gaps to maintain 50-Ohms. Here are two of the footprints, with 10-mil and 40-mil gaps. These views don't really show the vias stitching the ground planes on the top and bottom layers. The plane is solid on the bottom layer.
In the animated GIF, you can see for the 40/10 footprint with 10-mil gaps, there's a very large capacitive (negative) dip at the footprint. As the gaps are increased, you eventually get an inductive (positive) bump. In between, at around 40/20, you get a minimum bumpiness at the footprint. There's still some wiggling of a few Ohms, and a large inductive bump before the footprint (inside the connectors). These are $0.20 SMA connectors, after all, which I don't expect much from.
I'm going to populate another PCB with $2 connectors and see what they look like.
The 11 GHz transistors weren't cutting it, so I had to step up to some silicon-germanium-carbon transistors with a transition frequency of 45 GHz. Luckily, I'm currently experiencing 2019, and such things exist now. These PCB images all look the same, but here is the board:
The circuit is very close to the previous one, except with a different footprint for the SOT-343 transistors and added sites for peaking inductors:
The output transistors are a pair of BFP740ESD's, $0.54 each in single quantities. R1 and R2 are again 100 Ohms, setting the output impedance. R3 is 75 Ohms. They're driven in this case from and ADCMP607 CML-output comparator. The rising output edge from the transistors is under 75 ps, with the falling edge under 70 ps.
The transitions from the comparator are a relatively slow 120 ps or so (the datasheet says 160 typical), and this may be limiting the output transitions from the transistors. I'm going to spin a PCB for a ADCMP572 comparator with 35 ps transitions to see how much faster the transistors will go. Even as-is, this is fast enough to move forward with the design.
The output impedance of the circuit is 100-Ohms, set by the collector resistors. When loaded by the 50-Ohm scope inputs, the outputs have a 1 V amplitude. This means they're 3V unloaded, which is exactly the design point: perfect.
With the PCB layout, there is enough stray inductance that I just replaced the lumped inductors with 0-Ohm resistors; anything more caused undesirable ringing.
The lousy look of the step is due to some reflections on the PCB. I rushed this one out, and made some layout mistakes. Maybe I'll take a little more time on the next one.
The transistors have a maximum Vce of 4.2 V, set by internal ESD protection devices. I was able to run the output stage at a supply voltage of around 5 V, by which time it had achieved maximum amplitude. At around 5.5 V, the output started to tear:
this example also had 6.8n peaking inductors on the board, which causes the overshoot and ringing. The interesting thing is the high-frequency noise, which could be avalanche breakdown of the ESD protection devices, high-frequency parasitic oscillations, or an artifact of the sampling oscilloscope interacting with the waveform. I think the lesson is to keep the supply voltage to 5 V or less, but this is enough to give the 3 V output swing.
The bottom line is that this $1 pair of transistors do a better job than the $10 laser diode drivers I had been using. It's amazing to me that you can get these kind of speeds with discrete transistors, but you can.
I finally got around to populating an updated version of the SY88022AL test board. The datasheet claims typical 25 ps (20-80%) edges driving 30 mA into a 25-Ohm load. I haven't seen that yet, but it's definitely closer than last time.
In this updated version, I drove the part with a faster CML-output comparator. The ADCMP572 has typical 20-80% edges of 35 ps, according to the datasheet. Of course, the CML outputs don't drive enough current for my needs, otherwise I could just use the comparator as the driver. This is a SiGe part, so I was a little worried about over-cooking it with the skillet reflow process, but it seems to have survived, which is nice, because they're $20 each. I may end up moving them from board to board for different tests :-)
Here's what the thing looks like -- simple, really. The comparator switches when the input crosses a threshold (set at 1V because the scope's clock output is 2V unloaded). For some reason when I made this board, I didn't use the internal 50-Ohm termination on the input pin. It doesn't seem to affect the operation since the clock output is properly back-terminated, but I'll use it next time, for sure. Then, I'll set the threshold at 500 mV. The CML outputs drive the input of the SY88022AL.
I used a ADCMP607 comparator last time, with much slower transition times of 160 ps. I was ultimately not able to get the edges out of that board better than around 70 ps, although I may re-visit it at this point.
Here's around the best output I could get from this version. The transition times are around 40 ps for 10-90%. Assuming a linear rise, this is roughly equivalent to 30 ps 20-80%. The datasheet claims 25 ps typical, and I could easily see losing a few ps in the cabling and connectors.
What bothers me about the output, though, is that I can only get these edge speeds for what I would consider very low output levels. I changed the output driver current to see what effect this would have
In this case, I adjusted the output current to yield a 250 mV output amplitude. The output is loaded with 74 Ohms (50 for the scope plus a 24-Ohm series resistor to match the 25-Ohm outputs to the 50-Ohm transmission lines), so this is only delivering 3.3 mA into the load.
The datasheet numbers are specified at 30 mA, although they specify a 25-Ohm load, which equates to a 750 mV swing.
In any case, with this output amplitude, the edge rate is 38 ps.
Here, I turned the current up to yield 500 mV outputs. This is equivalent to 6.6 mA into the 75-Ohm load. The edg rates have dropped to 44 ps.
At 750 mV output swing, equivalent to 9.9 mA into the load, the edge rates are now 51 ps.
Finally, at a 1 V output swing, the edge rate has increased to 68 ps. This is 13.2 mA into the load.
At this level or higher, the output starts to take on a different character - you can see the second, slow, slope in the falling edge. This may be where the output drivers have hit their compliance-range limit, although that really shouldn't happen until around 2 V outputs, according to the datasheet. Below these levels, the relationship between the output levels and transition times seems roughly linear, implying a slew-rate limiting. You can see it in the following plot, where a line had been fit to the lower three levels, with the 1 V output clearly an outlier.
This model implies there's some fixed lower limit for the transition times, and that the edges have a fixed slew rate. That slew rate is around 10 kV/us, which is staggeringly fast.
There's still something funny going on here, but I'm not exactly sure what. Maybe I need to revisit the previous version having had this experience.
So, after the last test with some through-hole BJTs, I spun a quick PCB to test faster SMD transistors. I had some BFU550A's on hand, which boast an 11 GHz ft compared to the 900-2000 MHz range of the KSP5179's. The output connectors are on the bottom of the board.
The test circuit uses an ADCMP607 CML-output comparator to generate the differential outputs to drive the pair. The unloaded CML outputs have a 800 mV swing and 50-Ohm impedance. I used 75 Ohms at R3, and 100 Ohms at R1 and R2, as I had before. The ADCMP607 has typical rise and fall times of 160 ps (10% - 90%) according to the datasheet. The output pair has their own supply, which I set to 7 V for the following tests, while the comparator runs on 3.3V.
I replaced C3 and C4 in this schematic with 1k resistors to act as 21:1 Z0 probes. This reduces loading effects and also divides the output voltage so that it can be measured on the sampling scope, which has a +/- 2 V input range.
I hooked both outputs to input channels of an SD-24 sampling head in the 11801B scope. The outputs don't look spectacular, but they are certainly faster than the earlier test. In this case, the measured rise time was around 565 ps.
The fall time is around 100 ps shorter, coming in at around 466 ps.
The edges have a definite RC look to them - they start off good, then kind of fall off at the end. There is also an annoying extra step out around 3 ns. This is a reflection caused by my cheap ebay cables - they're around 47 Ohms instead of 50, which results in this kind of nonsense. I was able to simulate this in LTspice, below.
When I threw this quick board together, I forgot about inductive peaking. If the slow transitions are indeed a consequence of an RC structure, adding an inductor in-line with the collector resistors can reduce the rise/fall times. Very roughly, the inductor allows the capacitive component to charge before loading the output with the resistance.
I put together a simulation in LTspice to experiment with inductor values for peaking the outputs. I also added the transmission lines on the PCB and to the scope to model the step effect seen on the bench. A SPICE macro model for the BFU550A is available, which includes the package parasitics, yielding a more accurate result. Unfortunately, the models aren't licensed for redistribution - if you want to use them, you'll have to download them yourself.
I also wrote some code using the LTspice .MEASURE statement to calculate the rise/fall times and slew rate of the outputs.
Based on some initial cut-and-try tests, I came up with 5.6 nH as a good value for the peaking inductor. Here you can see runs with no inductor (1 fH), 5.6 nH, and 8.2 nH.
You can also see the later step caused by a simulated 47-Ohm output cable. Setting the impedance of this transmission line to 50-Ohms eliminates the step.
Zoomed in, you can see that without an inductor, the rise definitely droops a bit, with the 5.6 nH, the output looks better, and by 8.2 nH, the output overshoots.
The measured rise and fall times also show the effect. The initial rise time of 434 ps is reduced to just under 300 ps by the 5.6 nH, with only around 25 ps more improvement going to 8.2 nH at the cost of more overshoot. On the other hand, overshoot is not likely to be problem for strobe pulses intended for diode sampling bridges -- it might even prove beneficial.
Measurement: trise step t90r-t10r 1 4.3427e-010 2 2.99055e-010 3 2.73687e-010
These simulation doesn't exactly match the bench tests in the no-inductor case. While simulations show a 434 ps rise time, I measured 565 ps on the scope. I'd like to see these numbers closer, but with all the non-modeled parasitics on the PCB, I'm not going to worry about it too much at this point. It might be something to revisit later.
T-coils could theoretically produce better results than a simple inductor, but their math is complicated, and they're not off-the-shelf components....Read more »
So, after evaluating all the parts I could find with fast edges, I've come to the conclusion that none of them are suitable for generating the strobe pulse required for a high-speed diode sampling head. The available parts - logic, comparators, and laser diode drivers - all have output swings which are too small. Time to use discrete transistors. At GHz speeds. Ugh.
I started with what I had on-hand: a pair of KSP5179 transistors. They're rated at a minimum transition frequency of 900 MHz, which is around three times as fast as your ordinary 2N3904. Still, they won't do for the real sampling head. I'm looking at some 12 GHz ones at the moment, with 45 GHz SiGe units as a backup in case 12 doesn't cut it. For now, though, these T0-92 dinosaurs will serve as a proof-of-concept.
In the current plan, a discrete-transistor differential output stage will be driven by the output of a CML comparator.
The first thing to do is to simulate a CML output swing without having to use a real CML part for testing. They're all blazingly fast, which would be wasted on these modest output transistors, and they only come in SMT packages. Instead, I added some resistors to transform the 0/3.3V CMOS outputs of a 74AC74 flip-flop into the 2.5/3.3V outputs (800 mV swing) of an unloaded CML output. The correct choice of resistor also provides a 50-Ohm output impedance like real CML. Those 180-Ohm and 68-Ohm resistors do the trick.
I calculated the resistor values based on an assumed 22-Ohm output impedance for the 74AC74. It's really lower than this, but close enough. Maxima made short work of the required algebra. This kind of thing used to mean a half-hour diversion, including re-doing the manual calculations to catch mistakes.
The output circuit is very simple. The two transistors are arranged as a differential pair. The bases are driven by the CML levels. The 75-Ohm and 100-Ohm resistors set the output stage current and voltage swing. This is a textbook diff-pair and it just works. Parasitics are probably bad on this layout, but there's not too much that can be done with these big through-hole parts. The pair is powered by a higher voltage than the CML stage, so it can have a larger voltage swing. That's the key thing that couldn't be done even with open-collector laser diode drivers; there are always protection diodes in the way.
Here's what the output looks like. The top two traces are the outputs from the collectors of the transistors in green and blue. The bottom trace (pink) is one of the CML outputs - it's probed with a normal 10x probe with a long ground lead, so it shows some waviness. The rise and fall times of the outputs are around 1.7 ns. A rough back of the envelope calculation says that 12 GHz transistors might bring this into the 130 ps range, assuming everything else coöperates.
This test used a 7-volt supply at Vcc, and produces a single-ended swing of around 2.9 V (5.8 V differential). I figure I need around a 6 V differential swing to drive a diode sampling bridge, so this is very close. A little tweaking of the output stage resistors would do it.
The output, like the input, rides on a high DC bias voltage. That's OK -- it will be AC-coupled to the diode bridge. It's also important to note that the transistors must be kept out of saturation, in other words, the base voltage must be less than the collector voltage. On the screen, the red trace must be below the other two. You can see that the output supply voltage could be reduced a bit here.
The outputs have built-in 1k resistors to make 21x Z0- probes when combined with 50-Ohm scope inputs. Luckily, the scope allows you to enter any number for the probe multiplier that you like. Note the 1.05 V/division scaling :-)
Zooming in, we can get a better look at the transitions. They're actually better than I would have expected - nice linear ramps.
The KSP5179 datasheet has a SPICE model, so I simulated...Read more »
This time around, it's a differential strobe pulse generator designed around two laser diode driver ICs. The SY88932L is intended for driving fiber-optic lasers at up to 4.25 Gbps. The key thing I wanted to test with this board was creating short pulses with clip lines. Using this technique, I was able to generate strobe pulses of 172 ps width. That's narrow enough for a 2 GHz sampling head.
The laser driver claims typical rise and fall times of 65 ps (20%-80%), and I've measured around 100 ps (10%-90%). I made a simpler breakout to test just the SY88932L, but due to a supply chain snafu, I ended up having to remove the part from that PCB to populate this one.
I like this part because the logic is simple and the outputs are open-collectors. Some laser diode drivers are internally terminated with resistors, or worse, some kind of active bullshit which interferes with using them as general-purpose drivers. I don't know how far above Vcc you can push the outputs - the datasheet claims they can only go to Vcc, but I'm guessing you could probably go a few hundred mV above before any protection diodes kicked in. I'd really love if these were just raw open collectors, but I don't think so. At some point, I'm going to have to add some really fast external transistors to boost the output swing. But for these early tests, this part works OK.
Here's the 172 ps strobe generator. The input is converted by an ADCMP607 comparator. This part has a single-resistor-controlled hysteresis level and CML outputs which can drive the other ICs directly. I've chosen the input threshold to suit the clock output of the 11801 sampling scope for convenient triggering. There are two SY88932L's on the board: the first one generates short differential pulses using clip lines, and the second is used as an output driver. This really is just a prototype/breakout PCB. It sucks when you have to spin a 4-layer PCB just for one test, but this isn't the kind of stuff you can do on a solderless breadboard :-) The clip lines are just marked in text annotations; to Eagle, they're just normal traces. More on the clip lines below.
This is the PCB, with the clip lines annotated. There's an LTspice simulation further down the page that shows more about how this works, but in a nutshell, transmission lines with shorted ends are used to define the pulse width. A current pulse into the open end of the line can only exist for as long as the pulse takes to travel the length of the line, reflect off the end, and return to cancel the original pulse. Since the CML signals are differential, two identical lines are required. In this case, the lines are just made with coplanar waveguide traces on the top of the PCB. The advantage of this technique is that the timing is easily controlled and stable.
Tektronix used this technique to control pulses generated by step recovery diodes in their 1960s-era oscilloscope sampling heads. I found one for $30 on ebay so I can do a teardown - schematics are available, but they don't tell the whole story *at all*.
LTspice has a transmission line component that makes modeling the important part of this circuit easy. The transmission lines on the left are the clip lines, while those on the right are just the connecting traces between the two ICs. The open-collector outputs of the laser driver are modeled with current sources. There's an internal 50-ohm termination (right) inside the driver's inputs. The clip line is AC terminated at the resting-state voltage of each line by a 50-Ohm resistor and shunt capacitor. This causes an inverted reflection from the end of the line.
The output of the simulation shows what's going on. One of the input current pulses is shown in the top (red trace). The leading edge of the pulse switches the output at first, but eventually, the reflection arrives to cancel it out. On the trailing edge of the input pulse,...Read more »
In the last log, I looked at a resistive (Z0) oscilloscope - and spectrum analyzer - probe I had been using for a while. That version used a small metal film through-hole resistor. To see how SMD parts would compare, I built and tested another version this morning. This would probably be a single-use probe soldered on a PCB, but the parts are cheap enough.
This version uses a 453-Ohm 0603 resistor for a 10:1 probe with an input impedance of around 500 Ohms. Specifically, this uses the cheapest resistor I could find, a Yaego RC0603FR-07453RL. I bought them from DigiKey, but search is broken on their site at the moment, so you get a Mouser link instead.
The response looks pretty good right away. The rise time is 25 ps, again, at the edge of what I can measure. There is a 20% overshoot, then a negative ripple that looks fairly well resolved by 100 ps. That indicates it might be a decent probe up to around 3.5 GHz.
I took a wild shot at simulating this in LTspice. I looked up some typical package parasitics for 0603 resistors, and modeled the probe as a parallel-wire transmission line. Using 1 mm diameter as the conductor and 4 mm as the spacing, the impedance of such a parallel-wire structure is about 250 Ohms. At a length of 5.5 mm in air, this transmission line should have an electrical length of 18 ps. This is the model I ended up with:
Hit with a 25 ps rise-time pulse, you get this response:
At least qualitatively, I can recognize the basic features of the response. There might be something to this approach.
I found that applying just the right amount of compensating capacitance with my finger could flatten out overshoot and turn this into a 10 GHz probe. Then, I wondered if the same could be done with an SMD capacitor. The smallest one I had in stock was an 0603 0.5 pF, so I soldered it on there to see what would happen. I broke the solderable contacts off of three resistors doing this. SMD components are not meant to take much force.
The result is definitely over-compensated: you can see the capacitive step. This also adds 50 ps to the rise time. Overall, not really an improvement. This is the sort of thing you do with PCB pads, not lumped-element components.
I have often used a Z0 (resistive) probe in the past, especially for fast digital logic. This consists of nothing more than a resistor at the end of a piece of coax. Combined with the 50-Ohm termination inside a high-speed oscilloscope, this creates a voltage divider that reduces the loading on the circuit under test. I finally got around to testing this type of probe with the new scope.
This particular version uses a Stackpole RNF18FTD453R 453-Ohm resistor on the end of a length of RG-316 coax. Cutting a pre-made cable in half creates two probes :-) The resistor provides a 10:1 divisor ratio. It loads the circuit with 500 Ohms. I also have 953-Ohm versions for 20:1 probes. The non-coaxial length of the resistor and shield is 13 mm in this case. It's a little long, and it shows in the performance.
I usually just solder these probes on whatever I want to probe, so for this test, I cut the legs off a SMA end-launch connector and soldered the probe on there.
The first test was to measure the step produced by the TDR pulse generator on an SD-24 head in a Tek 11801 oscilloscope. The sampling head is spec'd with a 17.5 ps rise time, while the pulse has a rise time guaranteed less than 30 ps. For this test, I generated a pulse on one channel, which is connected to the modified SMA jack, and measured it through the Z0 probe on another channel.
The probe shows a 21 ps rise time, which is at the limits of my equipment, but experiences a really bad overshoot (~100%) that takes around 150 ps to fall back to where it should be. This overshoot is caused by the inductive impedance bump of the resistor and shield run through air.
Just to see how much of this was caused by the probe and how much by the SMA connector (a particularly cheap one), I tried the test in reverse, using the SMA jack side as the probe and the resistor/cable side as the probe. I offset the traces horizontally and vertically so you could compare them, since they are basically identical. The most telling evidence was that touching the resistor with a finger caused the same kind of perturbation, indicating that this was indeed the probe and not the SMA connection.
I will repeat this with an SMA M-M coupler at some point to see what that looks like.
I also tried looking into the probe with the TDR capabilities of the scope. In this case, a pulse is send in reverse down the probe coax, and any reflection(s) are observed. It's important to note that because these are reflections, the timescale is stretched by 2x.
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I added both screen shots so you can see that the impedance - note the vertical scale is in Ohms - does eventually rise to 500 Ohms, the level of the top cursor. The bottom cursor is 50 Ohms.
The 13 mm resistor length is about 43 ps electrically, assuming an air dielectric. So, the round-trip reflection of the end of the probe tip should be around 86 ps after the end of the coax. This is roughly at the first little bump in the response, so that kinda makes sense. I'm not sure what to make of this data, really. Can anyone lend a clue?
I had some 2-layer boards made to test assumptions about coplanar-waveguide (CPWG) over ground plane traces. I also used this test to explore issues with SMA-connector footprints.
I understand that this is just normal "random" FR-4 substrate, whose properties can vary widely, but the CPWG structure doesn't seem extremely sensitive to dielectric constant changes in the substrate. It does appear to be sensitive to the soldermask, though, for reasons I'll get into below.
I tested two CPWG geometries, both of which calculate out to 50-Ohms on (most) trace impedance calculators. The first, which seems relatively popular, has a 32-mil trace with 6-mil gaps to the top ground plane on either side; there's a solid ground plane on the bottom of the board. I also tested two different SMA footprints on these traces. One uses the same old footprint I had been using, which has a capacitive impedance bump due to the thick center pin of the SMA connector, while the other has some of the top ground plane cut away -- with a knife -- to compensate.
You can see a whole bunch of stuff in the annotated TDR trace below. Starting from the left, we first see the RG-316 cable, which measures out as 48.42 ohms (it's spec'd 50 +/- 2). Next, there's an inductive (positive) bump due to the mated SMA connectors. After that, there's the PCB footprint for the connector. In my old footprint, you can see a large capacitive (negative-going) bump, while in the cut-away version, you can see I removed too much copper. Back to work on that one.
The central flat portions are the traces themselves. Without soldermask, the trace measures 52.0 Ohms, while adding the mask brings it down to 48.4 Ohms. Both traces would have more than 34 dB return loss, and are actually within the tolerance for common "50-Ohm" cables, so they're probably equally fine for all but the most critical uses.
It's very interesting that the soldermask makes a difference of 3.6 Ohms in this case, though. I think what's happening is that because the ground plane is so far away in the 2-layer board compared to the side gaps (60 mils vs 6 mils), a lot of the energy is carried in the gaps rather than the substrate. So, adding soldermask with a dielectric constant of around 3 into the gap makes a big difference. I would expect the effect to be smaller where the gap-to-thickness ratio was smaller, like in 4-layer boards, or traces with wider gaps.
Here's another CPWG structure that calculators put at 50 Ohms, this one with wider gaps.
Again, the bottom trace is without soldermask and the top trace has it applied - ignore the trace colors, they are opposite from the plot above. As expected, the wider gap means that the soldermask has less influence on the characteristic impedance, in this case 2.2 Ohms vs the 3.6 Ohms for the 32/6 structure. Again, both these traces are perfectly good "50 Ohm" equivalents, so it really shouldn't make much difference. Unless your design rules don't support 6-mil gaps, there's probably no reason to use a 41/8 trace, unless you need a 41-mil wide solder pad for some component.
One of the places you might need a 41-mil solder pad is on edge-launch connectors. Some of them have wide pins that need a pad wider than 32 mils. The problem, though, is that the round pin itself introduces some capacitance. This can be seen as a dip in the TDR trace. For two of these tests (the outer SMA jacks on the left and right sides in the image below), I used my "standard" SMA footprint, which has a 41-mil wide trace for soldering the pin, and 8-mil wide gaps. Without the pin there, this is just the 41/8 CPWG tested above - you can see this on the rightmost jack, where the trace seems to got right to the board edge.
For the center two, I tried cutting away some of the ground plane on either side to widen the...Read more »
I designed this circuit two months ago, but had no way to test it until recently. The goal was to create a 350 ps differential strobe pulse for driving a diode sampling gate (a 1 GHz bandwidth sampler). I populated the board late last night, and it only took an hour this morning to figure out one of the ICs was backwards :-)
The board on the right is a termination so that I can look at the output with a 50-Ohm oscilloscope input. Shorting the PECL outputs directly into 50 Ohms tends to burn them out :-) Even with the seemingly short interconnects here, this still generates some reflections, which you can see in the second trace below. Those SMA adapters aren't short from the circuit's point of view.
So, here's the output: a 338 ps pulse. The silkscreen on the PCB says 350, so I'm only off by 12 ps, or 3.5%. I'm pretty happy with the result. The amplitude isn't calibrated correctly here, since the output is attenuated by the terminator and the trigger pickoff delay line - did I do a log about that yet? Anyway, the outputs are differential, so there's also a negative-going pulse similar to this one.
On a larger timescale, you can see the reflections caused by the poor termination. In the actual system, these lines would be properly terminated at the receiver, probably eliminating these bumps. In any case, these aren't likely to be large enough to bias the sampling diodes into conduction, so they don't matter, anyway.
The uses the difference in length between two differential pairs to determine the output pulse width. An SY100EPT22 translator converts the LVCMOS input into 3.3V LVPECL outputs. This output is duplicated by an SY100EP1U 2:1 fan-out buffer. The 20 ps maximum output skew on this part could account for my 12 ps error. The two outputs then feed into an MC100EP05 AND/NAND gate, but one of them is delayed by going through longer traces on the PCB. On each incoming pulse edge, the output goes high briefly, until the delayed signal comes along to turn it back off again.
All of the pullups are 127 Ohms, and the pulldowns 82.5 Ohms, which is the Thevenin equivalent of terminating the lines in 50 Ohms to Vcc-2 V (for a 3.3V supply). The resistors dissipate more heat than you might expect - unless you've done the math, that is.
The output driver has a typical rise/fall time of 220 ps, which ultimately limits the minimum pulse width. You can try to make it shorter than this, but then the amplitude of the pulse starts to drop.
Here you can see the lines that determine the pulse width. The red traces are on the top of the 4-layer PCB, while the blue ones are on the bottom.
With a dielectric constant of 3.66, the OSH Park 4-layer process should have a velocity factor of 0.523, so signals should travel at 1.568e8 m/s. This is equivalent to a delay of 162 ps/inch. The shorter red pair is 492 mils long, while the longer blue one is 2643 mils long, for a difference of 2151 mils. This equals a delay of 348 ps, so hey, I'm only really 10 ps off!
The original plan was to use a pulse generator like this for a sampling head strobe. I'll probably still build one using this design, but have shifted my attention to pulse generators using inexpensive laser diode drivers instead. The PECL gates on this PCB are expensive, power hungry, and ultimately too slow for where I want to go. As a demonstration, it's not bad, and it's probably still worth developing into a full sampling head just for the experience, but there's no future in it.
On the other hand, this board validated a bunch of assumptions and techniques that I'll need later.