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# RELAY COMPUTING

computer science + relay technology

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My ultimate goal is to build a relay-based version of my SANX-I microcomputer:

# 1-bit gates.

AND, OR, XOR, NOT

S = NOT A * (NOT Ci * B + Ci * NOT B) + A * (NOT Ci * NOT B + Ci * B)

Co = NOT A * Ci * B + A * (NOT Ci * B + Ci)

Note:  (NOT Ci * B + Ci) = B + Ci

Phase #1: design & simulation.

Phase #1: design & simulation.

# T flip-flop.

Phase #1: design & simulation.

# Asynchronous (ripple) binary counter.

Phase #1: design & simulation.

# 1-bit register connected to a bus.

When WRITE changes from 1 to 0, the value on the bus is stored in the register. When READ is 1, the value stored in the register is transferred along the bus.

Phase #1: design & simulation.

# 1-bit memory: MEM[X,Y].

Phase #1: design & simulation.

# 4 to 16 decoder.

Phase #1: design & simulation.

Note: requires SPDT digital model 2.

• ### SPDT solely

Javier Piay (PROPHYCOM)01/10/2019 at 11:08 0 comments

I'm aware of other great relay computing designs using multi-pole relays and/or other components like resistors, capacitors and diodes. I will try to use SPDT relays solely and avoid race/hazard conditions. I use pull-down resistors for simulation purposes and to couple relays with electronics, but these resistors are not part of the logic circuit.

Let's see how far I can go...

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## Discussions

Javier Piay (PROPHYCOM) wrote 6 days ago point

Well, that's the easy part ;)

#SANX-I MICROCOMPUTER

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Yann Guidon / YGDES wrote 6 days ago point

For the ALU, have a look at   #Simple Relay ALU  :-)

it uses diodes but it's pretty smart !

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Javier Piay (PROPHYCOM) wrote 6 days ago point

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Yann Guidon / YGDES wrote 01/10/2019 at 04:23 point

That first relay ripple counter looks... complicated :-P
This one has only 2 relays per stage : https://www.youtube.com/watch?v=BE2F9dvAI-Q

The relevant log is there : https://hackaday.io/project/159762-hardware-assembler-emui/log/155764-binary-counterdivider-with-relays

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Sophi Kravitz wrote 01/10/2019 at 03:53 point

Are you sure? yes | no

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