Close
0%
0%

HDMI to FPGA to APA102

132 APA102 LED panels, 680 pixels per panel, 90,000 pixels, 300sqft, 4 Spartan 6 Mojo FPGAs

Similar projects worth following
LED Wall at Oregon Museum of Science & Industry: https://photos.app.goo.gl/8hZoa7y9F9Lsg7Md9 (animation credit to yassi @ openprocessing.org)The creative director wanted to put the LED display behind a wood grain pattern similar to the wall at Microsoft HQ. When the LEDs are off the visitor sees a seemless, unobtrusive wall. To make the LEDs pop behind the wood grain graphic we used a very brigtht APA102.The resolution is about 24' wide by 14' high. That's 408 pixels wide 220 pixels tall. Not quite VGA. The FPGA's boards are Spartan-6 on a Mojo development platform: https://alchitry.com/

Oregon Museum of Science & Industry (OMSI) - giant LED wall


132 APA102 LED panels, 680 pixels per panel, 90,000 pixels, 300sqft, 4 Spartan 6 Mojo FPGAs

Source files on github

LED Wall at Oregon Museum of Science: https://photos.app.goo.gl/8hZoa7y9F9Lsg7Md9 (animation credit to yassi @ openprocessing.org)

The creative director wanted to put the LED display behind a wood grain pattern similar to the wall at Microsoft HQ. When the LEDs are off the visitor sees a seemless, unobtrusive wall. To make the LEDs pop behind the wood grain graphic we used a very brigtht APA102.

The resolution is about 24' wide by 14' high. That's 408 pixels wide 220 pixels tall. Not quite VGA. 

The FPGA's boards are Spartan 6 on a Mojo development platform: https://alchitry.com/ The wall is broken down into 4 sections for 4 Mojo's and each Mojo receives the same HDMI signal but only grabs pixels for the section of LEDs it controls. 

Alchitry has an HDMI shield for the Mojo and the FPGA code is written in their programming environment in Lucid a form of Verilog. It's great for beginners. This was my first FPGA project.

The HDMI signal is decoded and pixels arranged for each panel in local memory (RAM). There is just enough memory to save about 30% of the pixels so it takes 3 passes to arrange and output all the pixels... 60HZ / 3 gives us 20 frames per second. Thanks to David Hulton and Devin Boyer for sharing their mad FPGA memory tricks at Toorcamp 2018.

The SPI clock speed for writing to the APA102 also has speed limits as we 'race the beam.' Here's a great article by Paul Stoffregen (teensy) on these limits. The gist is the clock signals start to deteriorate between the pixels. For the 680 LEDs in our panel, I was able to write confidently at 6.25 MHZ. You can see how this clock signal is generated in any one of the 32 SPI modules in the source file under Mojo.

The FPGA generates an SPI clock and data signal to each LED panel. The signals are immediately fed from a simple shield to another custom PCB with RS485 transmitters shown above. The transmitter chips output differential signal pairs that pass easily in ethernet cords over 20-30 feet to each panel location. At the LED panel, the signals are received with transceiver chips back into clock and data lines and connected to their respective LED panel. This custom PCB also has a small DC-DC voltage transformers that take a 45VDC buss down to the 5V required for the LEDs.  The below PCB has tranceiver chips and three DC-DC transformers serving 3 LED panels. Thanks to the hardware maverick Tom Moxon with Pattern Agents for help designing this circuit.

The led panels themselves are little more than strip LEDs that have been connected together.  We had them customized for our particular geometry by our favorite supplier Raywu.

Mojo HDMI Shield: https://embeddedmicro.com/products/hdmi-shield

This design builds off of a lucid module example for decoding HDMI signals: https://embeddedmicro.com/blogs/tutorials/hdmi-shield-basics

Custom Circuit Boards

We used 3 types of circuit boards.
* A simple shield for the mojo that broke out all the SPI and Clock signals to the LED panels.
* A transmitter board that sends the clock and data signal out over RS485
* A receiver board that has transceiver chips, takes the signals 

Mojo Shield has all the pins broken out. We needed 33 SPI Data pins and the clock pin was shared across all the Panels.  The pins are broken out to 5.08mm phoenix connectors. The HDMI shield fits on the Mojo and this shield connects ontop of the HDMI shield. Oshpark boards here. See github for source files.

The transmitter board takes two SPI signals...

Read more »

FPGA_overview2.JPG

The HDMI signal is decoded and pixels arranged for each panel in local memory (RAM). There is just enough memory to save about 30% of the pixels so it takes 3 passes to arrange and output all the pixels... 60HZ / 3 gives us 20 frames per second. Thanks to David Hulton and Devin Boyer for sharing their mad FPGA memory tricks at Toorcamp 2018.

JPEG Image - 157.13 kB - 01/31/2019 at 04:13

Preview
Download

transmitter_schematic.JPG

The transmitter board takes two SPI signals (Clock and Data) and passes the signals through an RS485 transmitter chip. The differential signals are routed to an ethernet jack. This board could have been integrated into the Mojo shield to reduce noise but my disigning, programming, prototyping, and installing timelines compressed the schedule and I had to learn as I went. Oshpark transmitter chip: Texas Instrument AM27LV31 296-24690-1-ND RJ45 ethernet jack: 380-1316-5-ND

JPEG Image - 104.41 kB - 01/31/2019 at 04:13

Preview
Download

receiver_schematic.JPG

The receiver board receives RS485 signals via a RJ485 ethernet jack. Converts the two differential pairs back into clock and data SPI signals and connects to one LED panel. The board also has a DC-to-DC converter that takes 45V to 5V to supply to the LED panel. I did not put the TVS protection diodes on the boards but added them on just the last few boards I made when troubleshooting noise issues. Also, in addition to the 120ohm termination resistors on the RS485 bus, the original boards have 4.7k pullup and pulldown resistors on the bus. Modern RS485 chips have whats called "failsafe" against idle(no Data) conditions that these resistors are meant to deter.... so I left them out of these last few single signal boards shown here. Oshpark

JPEG Image - 102.24 kB - 01/31/2019 at 04:13

Preview
Download

JPEG Image - 92.80 kB - 01/30/2019 at 02:19

Preview
Download

JPEG Image - 198.82 kB - 01/30/2019 at 02:19

Preview
Download

View all 8 files

  • 20FPS

    thomas01/31/2019 at 04:03 0 comments

    The LED wall went live in the fall of 2018 but other projects kept me from fixing a few bugs. I felt compelled to fix them before publishing. The frame rate last year was abysmal. I got help from a few wizard FPGA designers at toorcamp 2018 managing the onboard memory.   We changed the way we wrote out to the LED panels and finally last week I got the frame rate up to 20fps.

View project log

Enjoy this project?

Share

Discussions

Dan Maloney wrote 01/30/2019 at 16:28 point

So how thin does the wood need to be to let the LEDs shine through that brightly?

  Are you sure? yes | no

thomas wrote 01/30/2019 at 17:58 point

Good question. So we tried a few different wood veneers but the typcal wood grain veneer available really messed with the color quality.  A similar LED wall at the Microsoft headquarters uses a sycamore veneer that doesn't effect color but was pretty expensive. We ended up going with a 1st surface graphic/wood-print on 1/4" milkplex. 

  Are you sure? yes | no

Similar Projects

Does this project spark your interest?

Become a member to follow this project and never miss any updates