thomas
FPGA_overview2.JPGThe HDMI signal is decoded and pixels arranged for each panel in local memory (RAM). There is just enough memory to save about 30% of the pixels so it takes 3 passes to arrange and output all the pixels... 60HZ / 3 gives us 20 frames per second. Thanks to David Hulton and Devin Boyer for sharing their mad FPGA memory tricks at Toorcamp 2018.JPEG Image - 157.13 kB - 01/31/2019 at 04:13 |
|
|
transmitter_schematic.JPGThe transmitter board takes two SPI signals (Clock and Data) and passes the signals through an RS485 transmitter chip. The differential signals are routed to an ethernet jack. This board could have been integrated into the Mojo shield to reduce noise but my disigning, programming, prototyping, and installing timelines compressed the schedule and I had to learn as I went. Oshparktransmitter chip: Texas Instrument AM27LV31 296-24690-1-ND RJ45 ethernet jack: 380-1316-5-ND JPEG Image - 104.41 kB - 01/31/2019 at 04:13 |
|
|
receiver_schematic.JPGThe receiver board receives RS485 signals via a RJ485 ethernet jack. Converts the two differential pairs back into clock and data SPI signals and connects to one LED panel. The board also has a DC-to-DC converter that takes 45V to 5V to supply to the LED panel. I did not put the TVS protection diodes on the boards but added them on just the last few boards I made when troubleshooting noise issues. Also, in addition to the 120ohm termination resistors on the RS485 bus, the original boards have 4.7k pullup and pulldown resistors on the bus. Modern RS485 chips have whats called "failsafe" against idle(no Data) conditions that these resistors are meant to deter.... so I left them out of these last few single signal boards shown here. OshparkJPEG Image - 102.24 kB - 01/31/2019 at 04:13 |
|
|
|
JPEG Image - 92.80 kB - 01/30/2019 at 02:19 |
|
|
|
JPEG Image - 198.82 kB - 01/30/2019 at 02:19 |
|
|
|
JPEG Image - 185.37 kB - 01/30/2019 at 02:19 |
|
|
|
JPEG Image - 142.08 kB - 01/30/2019 at 02:19 |
|
|
|
JPEG Image - 78.51 kB - 01/30/2019 at 02:19 |
|
|
HDMI to FPGA to APA102
132 APA102 LED panels, 680 pixels per panel, 90,000 pixels, 300sqft, 4 Spartan 6 Mojo FPGAs